Visible to Intel only — GUID: qow1490841686989
Ixiasoft
Single-Ended I/O Standard Specifications
Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
Single-Ended SSTL and HSTL I/O Standards Signal Specifications
Differential SSTL I/O Standard Specifications
Differential HSTL I/O Standard Specifications
Differential I/O Standard Specifications
Visible to Intel only — GUID: qow1490841686989
Ixiasoft
Mini-LVDS Transmitter Timing Specifications
Symbol | Modes | C6 | I7 | C8, A7 | I8 | Unit | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |||
fHSCLK (input clock frequency) | ×10 | 5 | — | 200 | 5 | — | 155.5 | 5 | — | 155.5 | 5 | — | 155.5 | MHz |
×8 | 5 | — | 200 | 5 | — | 155.5 | 5 | — | 155.5 | 5 | — | 155.5 | MHz | |
×7 | 5 | — | 200 | 5 | — | 155.5 | 5 | — | 155.5 | 5 | — | 155.5 | MHz | |
×4 | 5 | — | 200 | 5 | — | 155.5 | 5 | — | 155.5 | 5 | — | 155.5 | MHz | |
×2 | 5 | — | 200 | 5 | — | 155.5 | 5 | — | 155.5 | 5 | — | 155.5 | MHz | |
×1 | 5 | — | 400 | 5 | — | 311 | 5 | — | 311 | 5 | — | 311 | MHz | |
Device operation in Mbps | ×10 | 100 | — | 400 | 100 | — | 311 | 100 | — | 311 | 100 | — | 311 | Mbps |
×8 | 80 | — | 400 | 80 | — | 311 | 80 | — | 311 | 80 | — | 311 | Mbps | |
×7 | 70 | — | 400 | 70 | — | 311 | 70 | — | 311 | 70 | — | 311 | Mbps | |
×4 | 40 | — | 400 | 40 | — | 311 | 40 | — | 311 | 40 | — | 311 | Mbps | |
×2 | 20 | — | 400 | 20 | — | 311 | 20 | — | 311 | 20 | — | 311 | Mbps | |
×1 | 10 | — | 400 | 10 | — | 311 | 10 | — | 311 | 10 | — | 311 | Mbps | |
tDUTY | — | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | 45 | — | 55 | % |
TCCS | — | — | — | 200 | — | — | 200 | — | — | 200 | — | — | 200 | ps |
Output jitter (peak to peak) | — | — | — | 500 | — | — | 500 | — | — | 550 | — | — | 600 | ps |
tRISE | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tFALL | 20 – 80%, CLOAD = 5 pF | — | 500 | — | — | 500 | — | — | 500 | — | — | 500 | — | ps |
tLOCK 43 | — | — | — | 1 | — | — | 1 | — | — | 1 | — | — | 1 | ms |
43 tLOCK is the time required for the PLL to lock from the end-of-device configuration.