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Ixiasoft
Single-Ended I/O Standard Specifications
Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
Single-Ended SSTL and HSTL I/O Standards Signal Specifications
Differential SSTL I/O Standard Specifications
Differential HSTL I/O Standard Specifications
Differential I/O Standard Specifications
Visible to Intel only — GUID: sng1487191161322
Ixiasoft
Pin Capacitance
Symbol | Parameter | Typical – Quad Flat Pack (QFP) | Typical – Ball-Grid Array (BGA) 18 | Unit |
---|---|---|---|---|
CIOTB | Input capacitance on top and bottom I/O pins | 7 | 6 | pF |
CIOLR | Input capacitance on right I/O pins | 7 | 5 | pF |
CLVDSLR | Input capacitance on right I/O pins with dedicated LVDS output | 8 | 7 | pF |
CVREFLR 19 | Input capacitance on right dual-purpose VREF pin when used as VREF or user I/O pin | 21 | 21 | pF |
CVREFTB 19 | Input capacitance on top and bottom dual-purpose VREF pin when used as VREF or user I/O pin | 23 20 | 23 | pF |
CCLKTB | Input capacitance on top and bottom dedicated clock input pins | 7 | 6 | pF |
CCLKLR | Input capacitance on right dedicated clock input pins | 6 | 5 | pF |
18 The pin capacitance applies to FBGA, UBGA, and MBGA packages.
19 When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin capacitance.
20 CVREFTB for the 10CL025 device is 30 pF.