Visible to Intel only — GUID: bhc1519721244715
Ixiasoft
Single-Ended I/O Standard Specifications
Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
Single-Ended SSTL and HSTL I/O Standards Signal Specifications
Differential SSTL I/O Standard Specifications
Differential HSTL I/O Standard Specifications
Differential I/O Standard Specifications
Visible to Intel only — GUID: bhc1519721244715
Ixiasoft
PS Configuration Timing
Symbol | Parameter | Minimum | Maximum | Unit | ||
---|---|---|---|---|---|---|
1.2 V Core Voltage | 1.0 V Core Voltage | 1.2 V Core Voltage | 1.0 V Core Voltage | |||
tCF2CD | nCONFIG low to CONF_DONE low | — | 500 | ns | ||
tCF2ST0 | nCONFIG low to nSTATUS low | — | 500 | ns | ||
tCFG | nCONFIG low pulse width | 500 | — | ns | ||
tSTATUS | nSTATUS low pulse width | 45 | 230 51 | µs | ||
tCF2ST1 | nCONFIG high to nSTATUS high | — | 230 52 | µs | ||
tCF2CK | nCONFIG high to first rising edge on DCLK | 230 51 | — | µs | ||
tST2CK | nSTATUS high to first rising edge of DCLK | 2 | — | µs | ||
tDH | Data hold time after rising edge on DCLK | 0 | — | ns | ||
tCD2UM | CONF_DONE high to user mode 53 | 300 | 650 | µs | ||
tCD2CU | CONF_DONE high to CLKUSR enabled | 4 × maximum DCLK period | — | — | ||
tCD2UMC | CONF_DONE high to user mode with CLKUSR option on | tCD2CU + (3,192 × CLKUSR period) | — | — | ||
tDSU | Data setup time before rising edge on DCLK | 5 | 8 | — | ||
tCH | DCLK high time | 3.2 | 6.4 | — | — | ns |
tCL | DCLK low time | 3.2 | 6.4 | — | — | ns |
tCLK | DCLK period | 7.5 | 15 | — | — | ns |
fMAX | DCLK frequency | — | — | 133 | 66 | MHz |
Related Information
51 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
52 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
53 The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.