Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
Public
Document Table of Contents

Bus Hold

The bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.
Table 6.   Bus Hold Parameter for Intel® Cyclone® 10 LP DevicesBus hold trip points are based on the calculated input voltages from the JEDEC standard.
Parameter Condition VCCIO (V) Unit
1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus hold low, sustaining current VIN > VIL (maximum) 8 12 30 50 70 70 μA
Bus hold high, sustaining current VIN < VIL (minimum) –8 –12 –30 –50 –70 –70 μA
Bus hold low, overdrive current 0 V < VIN < VCCIO 125 175 200 300 500 500 μA
Bus hold high, overdrive current 0 V < VIN < VCCIO –125 –175 –200 –300 –500 –500 μA
Bus hold trip point 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V