Visible to Intel only — GUID: jbr1444155365095
Ixiasoft
2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
Visible to Intel only — GUID: jbr1444155365095
Ixiasoft
2.7. Full Compilation Flow
Use these steps to run a full compilation of an Intel® Quartus® Prime project. A full compilation includes IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and any optional Compiler modules you enable.
- Before running a full compilation, specify any of the following project settings:
- To specify the target FPGA device or development kit, click Assignments > Device.
- To specify device and pin options for the target FPGA device, click Assignments > Device > Device and Pin Options.
- To specify options that affect compilation processing time and netlist preservation, click Assignments > Settings > Compilation Process Settings.
- To specify the Compiler's high-level optimization strategy, click Assignments > Settings > Compiler Settings. Specify a Balanced strategy, or optimize for Performance, Area, Routability, Power, or Compile Time. The Compiler targets the optimization goal you specify. Compiler Optimization Modes describes these options in detail.
- To specify synthesis algorithm and other Advanced Settings for synthesis and fitting, click Assignments > Settings > Compiler Settings. Turn on Enable Intermediate Fitter Snapshots to preserve the planned, placed, routed, and retimed snapshots by default during full compilation.
- To specify required timing conditions for proper operation of your design, click Tools > Timing Analyzer.
- To run full compilation, click Processing > Start Compilation.
Note:
- To save processing time, the Compiler only preserves the planned, placed, routed, and retimed snapshots during full compilation if you turn on Enable Intermediate Fitter Snapshots (Assignments > Settings > Compiler Settings).