Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 1/27/2022
Public

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2.7. Full Compilation Flow

Use these steps to run a full compilation of an Intel® Quartus® Prime project. A full compilation includes IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and any optional Compiler modules you enable.
  1. Before running a full compilation, specify any of the following project settings:
    • To specify the target FPGA device or development kit, click Assignments > Device.
    • To specify device and pin options for the target FPGA device, click Assignments > Device > Device and Pin Options.
    • To specify options that affect compilation processing time and netlist preservation, click Assignments > Settings > Compilation Process Settings.
    • To specify the Compiler's high-level optimization strategy, click Assignments > Settings > Compiler Settings. Specify a Balanced strategy, or optimize for Performance, Area, Routability, Power, or Compile Time. The Compiler targets the optimization goal you specify. Compiler Optimization Modes describes these options in detail.
    • To specify synthesis algorithm and other Advanced Settings for synthesis and fitting, click Assignments > Settings > Compiler Settings. Turn on Enable Intermediate Fitter Snapshots to preserve the planned, placed, routed, and retimed snapshots by default during full compilation.
    • To specify required timing conditions for proper operation of your design, click Tools > Timing Analyzer.
  2. To run full compilation, click Processing > Start Compilation.
    Note:
    • To save processing time, the Compiler only preserves the planned, placed, routed, and retimed snapshots during full compilation if you turn on Enable Intermediate Fitter Snapshots (Assignments > Settings > Compiler Settings).