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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.11.3. Automatic Gated Clock Conversion
Clock gating saves power in ASIC designs by adding more logic to a circuit to prune the clock tree. Pruning the clock tree disables portions of the circuitry so that the flip-flops are not required to switch states. When using an Intel® Quartus® Prime FPGA to prototype ASIC designs, you must convert clock gates to clock enables in your design.
ASIC Gated Clock Example | FPGA Clock Enable Example |
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Rather than manually converting gated clocks in your RTL, you can specify the Auto Gated Clock Conversion setting to automatically convert gated base clocks in the design to clock enables. You can apply this setting globally to all gated base clocks in the design, or to one or more specific clock signals.
Setting Scope |
Description |
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Global | Enable the Auto Gated Clock Conversion option at Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Alternatively, add the global assignment to the project .qsf: |
Instance-specific | Specify the Auto Gated Clock Conversion for one or more instances in the Assignment Editor (Assignments > Assignment Editor). Alternatively, add the instance assignment to the project .qsf: |
Following design synthesis, view the results of gated clock conversion in the Gated Clock Conversion Details report. The report lists all converted and unconverted gated clocks with their base clocks. For unconverted gated clocks, the report specifies the reason the clock is not converted.
Note: Automatic gated clock conversion supports explicit RAMs (such as WYSIWYG RAMs and Intel FPGA memory IP), but does not support inferred RAMs.
Figure 59. Gated Clock Conversion Details Report