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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.10.1.5. Verilog HDL Macros
The Intel® Quartus® Prime software fully supports Verilog HDL macros, which you can define with the 'define compiler directive in your source code. You can also define macros in the Intel® Quartus® Prime software or on the command line.
To set Verilog HDL macros at the command line for the Intel® Quartus® Prime Pro Edition synthesis (quartus_syn) executable, use the following format:
quartus_syn <PROJECT_NAME> --set=VERILOG_MACRO=a=2
This command adds the following new line to the project .qsf file:
set_global_assignment -name VERILOG_MACRO "a=2"
To avoid adding this line to the project .qsf, add this option to the quartus_syn command:
--write_settings_files=off