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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.5.2.1.2. Analyzing Clocking with Snapshot Viewer
This task is available only for Intel® Stratix® 10 devices.
- Run the Place stage, and then click the Snapshot Viewer icon for the stage in the Compilation Dashboard. The Snapshot Viewer opens.
- Under Analyze Clocking, double-click Show Global Clock Visualization. The Global Signal Visualization report displays in Snapshot Viewer for analysis of clock sector and routing utilization.
Figure 24. Global Clock Visualization Report