ID
683236
Date
1/27/2022
Public
Visible to Intel only — GUID: faq
Ixiasoft
2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
Visible to Intel only — GUID: faq
Ixiasoft
1. Answers to Top FAQs
Updated for: |
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Intel® Quartus® Prime Design Suite 21.4 |
How can my signals persist through synthesis? |
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How can I optimize my design in stages? |
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How do I optimize for high-performance devices? |
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What retiming restrictions limit performance? |
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Can I transfer projects between software versions? |
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How do I divide a project into partitions? |
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How do I add other EDA tools to the flow? |
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Can I target speed, area, power, or run time? |
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How can I reduce the compilation time? |