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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.1. Compilation Overview
The Compiler is modular, allowing you to run only the process that you need. Each Compiler module performs a specific function in the full compilation process. When you run any module, the Compiler runs any prerequisite modules automatically and generates detailed reports at each stage. The Compiler can preserve a "snapshot" of the compilation results after each stage.
Compilation Process | Description |
---|---|
IP Generation | Identifies the status and version of IP components in the project. Reports outdated IP that require upgrade. |
Analysis & Synthesis | Synthesizes, optimizes, minimizes, and maps design logic to device resources. The "synthesized" snapshot preserves the results of this stage. Analysis & Elaboration is a stage of Analysis & Synthesis. This stage checks for design file and project errors. |
Fitter (Place & Route) | Assigns the placement and routing of the design to specific device resources, while honoring timing and placement constraints. The Fitter includes the following stages:
|
Fast Forward Timing Closure Recommendations | Generates detailed reports that estimate performance gains achievable by making specific RTL modifications. |
Timing Analysis | Analyzes and validates the timing performance of all design logic with the Timing Analyzer. |
Power Analysis | Optional module that estimates device power consumption. Specify the electrical standard on each I/O cell and the board trace model on each I/O standard in your design. |
Assembler | Converts the Fitter's placement and routing assignments into a programming image for the FPGA device. |
EDA Netlist Writer | Generates output files for use in other EDA tools, as Integrating Other EDA Tools describes. |
Note: Each successive release of the Intel® Quartus® Prime software typically includes:
- Added support for new features in supported FPGA devices.
- Added support for new devices.
- Efficiency and performance improvements.
- Improvements to compilation time and resource use of the design software.
1 Retiming and Fast Forward compilation available only for Intel® Stratix® 10 and Intel® Agilex™ devices.