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1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices
2. Embedded Memory Blocks in Arria V Devices
3. Variable Precision DSP Blocks in Arria V Devices
4. Clock Networks and PLLs in Arria V Devices
5. I/O Features in Arria V Devices
6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices
7. External Memory Interfaces in Arria V Devices
8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices
9. SEU Mitigation for Arria V Devices
10. JTAG Boundary-Scan Testing in Arria V Devices
11. Power Management in Arria V Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Arria V Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Error Correction Code Support
2.11. Embedded Memory Blocks in Arria V Devices Revision History
3.6.1.1. 9 x 9 Independent Multiplier
3.6.1.2. 18 x 18 Independent Multiplier
3.6.1.3. 18 x 18 or 18 x 19 Independent Multiplier
3.6.1.4. 16 x 16 Independent Multiplier or 18 x 18 Independent Partial Multiplier
3.6.1.5. 18 x 25 Independent Multiplier
3.6.1.6. 20 x 24 Independent Multiplier
3.6.1.7. 27 x 27 Independent Multiplier
3.6.1.8. 36 x 18 Independent Multiplier
3.6.1.9. 36-Bit Independent Multiplier
4.2.1. PLL Physical Counters in Arria V Devices
4.2.2. PLL Locations in Arria® V Devices
4.2.3. PLL Migration Guidelines
4.2.4. Fractional PLL Architecture
4.2.5. PLL Cascading
4.2.6. PLL External Clock I/O Pins
4.2.7. PLL Control Signals
4.2.8. Clock Feedback Modes
4.2.9. Clock Multiplication and Division
4.2.10. Programmable Phase Shift
4.2.11. Programmable Duty Cycle
4.2.12. Clock Switchover
4.2.13. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O Resources Per Package for Arria® V Devices
5.2. I/O Vertical Migration for Arria® V Devices
5.3. I/O Standards Support in Arria V Devices
5.4. I/O Design Guidelines for Arria V Devices
5.5. I/O Banks Locations in Arria® V Devices
5.6. I/O Banks Groups in Arria V Devices
5.7. I/O Element Structure in Arria V Devices
5.8. Programmable IOE Features in Arria V Devices
5.9. On-Chip I/O Termination in Arria V Devices
5.10. External I/O Termination for Arria V Devices
5.11. I/O Features in Arria V Devices Revision History
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.4.2. Guideline: Use the Same VCCPD for All I/O Banks in a Group
5.4.3. Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank
5.4.4. Guideline: VREF Pin Restrictions
5.4.5. Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing
5.4.6. Guideline: Use PLL Integer Mode for LVDS Applications
5.4.7. Guideline: Pin Placement for General Purpose High-Speed Signals
5.8.1. Programmable Current Strength
5.8.2. Programmable Output Slew Rate Control
5.8.3. Programmable IOE Delay
5.8.4. Programmable Output Buffer Delay
5.8.5. Programmable Pre-Emphasis
5.8.6. Programmable Differential Output Voltage
5.8.7. Open-Drain Output
5.8.8. Pull-up Resistor
5.8.9. Bus-Hold Circuitry
6.1. Dedicated High-Speed Circuitries in Arria® V Devices
6.2. High-Speed I/O Design Guidelines for Arria® V Devices
6.3. Differential Transmitter in Arria V Devices
6.4. Differential Receiver in Arria V Devices
6.5. Source-Synchronous Timing Budget
6.6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices Revision History
7.4.1. UniPHY IP
7.4.2. External Memory Interface Datapath
7.4.3. DQS Phase-Shift Circuitry
7.4.4. Phase Offset Control for Arria® V GZ Devices
7.4.5. PHY Clock (PHYCLK) Networks
7.4.6. DQS Logic Block
7.4.7. Leveling Circuitry for Arria V GZ Devices
7.4.8. Dynamic OCT Control
7.4.9. IOE Registers
7.4.10. Delay Chains
7.4.11. I/O and DQS Configuration Blocks
7.5.1. Features of the Hard Memory Controller
7.5.2. Multi-Port Front End
7.5.3. Bonding Support
7.5.4. Hard Memory Controller Width for Arria V GX
7.5.5. Hard Memory Controller Width for Arria V GT
7.5.6. Hard Memory Controller Width for Arria V SX
7.5.7. Hard Memory Controller Width for Arria V ST
8.1. Enhanced Configuration and Configuration via Protocol
8.2. MSEL Pin Settings
8.3. Configuration Sequence
8.4. Configuration Timing Waveforms
8.5. Device Configuration Pins
8.6. Fast Passive Parallel Configuration
8.7. Active Serial Configuration
8.8. Using EPCS and EPCQ Devices
8.9. Passive Serial Configuration
8.10. JTAG Configuration
8.11. Configuration Data Compression
8.12. Remote System Upgrades
8.13. Design Security
8.14. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Revision History
10.1. BST Operation Control
10.2. I/O Voltage for JTAG Operation
10.3. Performing BST
10.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
10.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
10.6. IEEE Std. 1149.1 Boundary-Scan Register
10.7. IEEE Std. 1149.6 Boundary-Scan Register
10.8. JTAG Boundary-Scan Testing inArria V Devices Revision History
11.1. Power Consumption
11.2. Programmable Power Technology
11.3. Temperature Sensing Diode
11.4. Hot-Socketing Feature
11.5. Hot-Socketing Implementation
11.6. Arria V GX, GT, SX, and ST Power-Up Sequence
11.7. Arria V GZ Power-Up Sequence
11.8. Power-On Reset Circuitry
11.9. Power Management in Arria V Devices Revision History
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4.1.7.3. RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® Prime software.
Figure 70. RCLK Control Block for Arria V Devices
You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus® Prime software using the ALTCLKCTRL IP core.
Note: When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1] ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.
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