Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

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ID 683213
Date 10/18/2023
Public
Document Table of Contents
Document Table of Contents x
1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices 2. Embedded Memory Blocks in Arria V Devices 3. Variable Precision DSP Blocks in Arria V Devices 4. Clock Networks and PLLs in Arria V Devices 5. I/O Features in Arria V Devices 6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices 7. External Memory Interfaces in Arria V Devices 8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices 9. SEU Mitigation for Arria V Devices 10. JTAG Boundary-Scan Testing in Arria V Devices 11. Power Management in Arria V Devices
1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices x
1.1. LAB 1.2. ALM Operating Modes 1.3. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices Revision History
1.1. LAB x
1.1.1. MLAB 1.1.2. Local and Direct Link Interconnects 1.1.3. LAB Control Signals 1.1.4. ALM Resources 1.1.5. ALM Output
1.2. ALM Operating Modes x
1.2.1. Normal Mode 1.2.2. Extended LUT Mode 1.2.3. Arithmetic Mode 1.2.4. Shared Arithmetic Mode
2. Embedded Memory Blocks in Arria V Devices x
2.1. Types of Embedded Memory 2.2. Embedded Memory Design Guidelines for Arria V Devices 2.3. Embedded Memory Features 2.4. Embedded Memory Modes 2.5. Embedded Memory Clocking Modes 2.6. Parity Bit in Memory Blocks 2.7. Byte Enable in Embedded Memory Blocks 2.8. Memory Blocks Packed Mode Support 2.9. Memory Blocks Address Clock Enable Support 2.10. Memory Blocks Error Correction Code Support 2.11. Embedded Memory Blocks in Arria V Devices Revision History
2.1. Types of Embedded Memory x
2.1.1. Embedded Memory Capacity in Arria V Devices
2.2. Embedded Memory Design Guidelines for Arria V Devices x
2.2.1. Guideline: Consider the Memory Block Selection 2.2.2. Guideline: Implement External Conflict Resolution 2.2.3. Guideline: Customize Read-During-Write Behavior 2.2.4. Guideline: Consider Power-Up State and Memory Initialization 2.2.5. Guideline: Control Clocking to Reduce Power Consumption
2.2.3. Guideline: Customize Read-During-Write Behavior x
2.2.3.1. Same-Port Read-During-Write Mode 2.2.3.2. Mixed-Port Read-During-Write Mode
2.3. Embedded Memory Features x
2.3.1. Embedded Memory Configurations 2.3.2. Mixed-Width Port Configurations
2.3.2. Mixed-Width Port Configurations x
2.3.2.1. M20K Blocks Mixed-Width Configurations 2.3.2.2. M10K Blocks Mixed-Width Configurations
2.5. Embedded Memory Clocking Modes x
2.5.1. Clocking Modes for Each Memory Mode 2.5.2. Asynchronous Clears in Clocking Modes 2.5.3. Output Read Data in Simultaneous Read/Write 2.5.4. Independent Clock Enables in Clocking Modes
2.5.1. Clocking Modes for Each Memory Mode x
2.5.1.1. Single Clock Mode 2.5.1.2. Read/Write Clock Mode 2.5.1.3. Input/Output Clock Mode 2.5.1.4. Independent Clock Mode
2.7. Byte Enable in Embedded Memory Blocks x
2.7.1. Byte Enable Controls in Memory Blocks 2.7.2. Data Byte Output 2.7.3. RAM Blocks Operations
2.10. Memory Blocks Error Correction Code Support x
2.10.1. Error Correction Code Truth Table
3. Variable Precision DSP Blocks in Arria V Devices x
3.1. Features 3.2. Supported Operational Modes in Arria V Devices 3.3. Resources 3.4. Design Considerations 3.5. Block Architecture 3.6. Operational Mode Descriptions 3.7. Variable Precision DSP Blocks in Arria V Devices Revision History
3.4. Design Considerations x
3.4.1. Operational Modes 3.4.2. Internal Coefficient and Pre-Adder 3.4.3. Accumulator 3.4.4. Chainout Adder
3.5. Block Architecture x
3.5.1. Input Register Bank 3.5.2. Pre-Adder 3.5.3. Internal Coefficient 3.5.4. Multipliers 3.5.5. Adder 3.5.6. Accumulator and Chainout Adder 3.5.7. Systolic Registers 3.5.8. Double Accumulation Register 3.5.9. Output Register Bank
3.6. Operational Mode Descriptions x
3.6.1. Independent Multiplier Mode 3.6.2. Independent Complex Multiplier Mode 3.6.3. Multiplier Adder Sum Mode 3.6.4. Sum of Square Mode 3.6.5. 18 x 18 Multiplication Summed with 36-Bit Input Mode 3.6.6. Systolic FIR Mode
3.6.1. Independent Multiplier Mode x
3.6.1.1. 9 x 9 Independent Multiplier 3.6.1.2. 18 x 18 Independent Multiplier 3.6.1.3. 18 x 18 or 18 x 19 Independent Multiplier 3.6.1.4. 16 x 16 Independent Multiplier or 18 x 18 Independent Partial Multiplier 3.6.1.5. 18 x 25 Independent Multiplier 3.6.1.6. 20 x 24 Independent Multiplier 3.6.1.7. 27 x 27 Independent Multiplier 3.6.1.8. 36 x 18 Independent Multiplier 3.6.1.9. 36-Bit Independent Multiplier
3.6.2. Independent Complex Multiplier Mode x
3.6.2.1. 18 x 18 Complex Multiplier 3.6.2.2. 18 x 19 Complex Multiplier 3.6.2.3. 18 x 25 Complex Multiplier 3.6.2.4. 27 x 27 Complex Multiplier
3.6.3. Multiplier Adder Sum Mode x
3.6.3.1. One Sum of Two 18 x 18 Multipliers or Two 16 x 16 Multipliers 3.6.3.2. One Sum of Two 18 x 19 Multipliers 3.6.3.3. One Sum of Two 27 x 27 Multipliers 3.6.3.4. One Sum of Two 36 x 18 Multipliers 3.6.3.5. One Sum of Four 18 x 18 Multipliers
3.6.6. Systolic FIR Mode x
3.6.6.1. 18-Bit Systolic FIR Mode 3.6.6.2. 27-Bit Systolic FIR Mode
4. Clock Networks and PLLs in Arria V Devices x
4.1. Clock Networks 4.2. Arria V PLLs 4.3. Clock Networks and PLLs in Arria V Devices Revision History
4.1. Clock Networks x
4.1.1. Clock Resources in Arria® V Devices 4.1.2. Types of Clock Networks 4.1.3. Clock Sources Per Quadrant 4.1.4. Types of Clock Regions 4.1.5. Clock Network Sources 4.1.6. Clock Output Connections 4.1.7. Clock Control Block 4.1.8. Clock Power Down 4.1.9. Clock Enable Signals
4.1.2. Types of Clock Networks x
4.1.2.1. Global Clock Networks 4.1.2.2. Regional Clock Networks 4.1.2.3. Periphery Clock Networks
4.1.4. Types of Clock Regions x
4.1.4.1. Entire Device Clock Region 4.1.4.2. Regional Clock Region 4.1.4.3. Dual-Regional Clock Region
4.1.5. Clock Network Sources x
4.1.5.1. Dedicated Clock Input Pins 4.1.5.2. Internal Logic 4.1.5.3. DPA Outputs 4.1.5.4. HSSI Outputs 4.1.5.5. PLL Clock Outputs 4.1.5.6. Clock Input Pin Connections to GCLK and RCLK Networks
4.1.7. Clock Control Block x
4.1.7.1. Pin Mapping in Arria V Devices 4.1.7.2. GCLK Control Block 4.1.7.3. RCLK Control Block 4.1.7.4. PCLK Control Block 4.1.7.5. External PLL Clock Output Control Block
4.2. Arria V PLLs x
4.2.1. PLL Physical Counters in Arria V Devices 4.2.2. PLL Locations in Arria® V Devices 4.2.3. PLL Migration Guidelines 4.2.4. Fractional PLL Architecture 4.2.5. PLL Cascading 4.2.6. PLL External Clock I/O Pins 4.2.7. PLL Control Signals 4.2.8. Clock Feedback Modes 4.2.9. Clock Multiplication and Division 4.2.10. Programmable Phase Shift 4.2.11. Programmable Duty Cycle 4.2.12. Clock Switchover 4.2.13. PLL Reconfiguration and Dynamic Phase Shift
4.2.4. Fractional PLL Architecture x
4.2.4.1. Fractional PLL Usage
4.2.7. PLL Control Signals x
4.2.7.1. areset 4.2.7.2. locked
4.2.8. Clock Feedback Modes x
4.2.8.1. Source Synchronous Mode 4.2.8.2. LVDS Compensation Mode 4.2.8.3. Direct Mode 4.2.8.4. Normal Compensation Mode 4.2.8.5. Zero-Delay Buffer Mode 4.2.8.6. External Feedback Mode
4.2.12. Clock Switchover x
4.2.12.1. Automatic Switchover 4.2.12.2. Automatic Switchover with Manual Override 4.2.12.3. Manual Clock Switchover 4.2.12.4. Guidelines
5. I/O Features in Arria V Devices x
5.1. I/O Resources Per Package for Arria® V Devices 5.2. I/O Vertical Migration for Arria® V Devices 5.3. I/O Standards Support in Arria V Devices 5.4. I/O Design Guidelines for Arria V Devices 5.5. I/O Banks Locations in Arria® V Devices 5.6. I/O Banks Groups in Arria V Devices 5.7. I/O Element Structure in Arria V Devices 5.8. Programmable IOE Features in Arria V Devices 5.9. On-Chip I/O Termination in Arria V Devices 5.10. External I/O Termination for Arria V Devices 5.11. I/O Features in Arria V Devices Revision History
5.2. I/O Vertical Migration for Arria® V Devices x
5.2.1. Verifying Pin Migration Compatibility
5.3. I/O Standards Support in Arria V Devices x
5.3.1. I/O Standards Support for FPGA I/O in Arria® V Devices 5.3.2. I/O Standards Support for HPS I/O in Arria V Devices 5.3.3. I/O Standards Voltage Levels in Arria® V Devices 5.3.4. MultiVolt I/O Interface in Arria® V Devices
5.4. I/O Design Guidelines for Arria V Devices x
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards 5.4.2. Guideline: Use the Same VCCPD for All I/O Banks in a Group 5.4.3. Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank 5.4.4. Guideline: VREF Pin Restrictions 5.4.5. Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing 5.4.6. Guideline: Use PLL Integer Mode for LVDS Applications 5.4.7. Guideline: Pin Placement for General Purpose High-Speed Signals
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards x
5.4.1.1. Non-Voltage-Referenced I/O Standards 5.4.1.2. Voltage-Referenced I/O Standards 5.4.1.3. Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
5.6. I/O Banks Groups in Arria V Devices x
5.6.1. Modular I/O Banks for Arria® V GX Devices 5.6.2. Modular I/O Banks for Arria® V GT Devices 5.6.3. Modular I/O Banks for Arria® V GZ Devices 5.6.4. Modular I/O Banks for Arria® V SX Devices 5.6.5. Modular I/O Banks for Arria® V ST Devices
5.7. I/O Element Structure in Arria V Devices x
5.7.1. I/O Buffer and Registers in Arria V Devices
5.8. Programmable IOE Features in Arria V Devices x
5.8.1. Programmable Current Strength 5.8.2. Programmable Output Slew Rate Control 5.8.3. Programmable IOE Delay 5.8.4. Programmable Output Buffer Delay 5.8.5. Programmable Pre-Emphasis 5.8.6. Programmable Differential Output Voltage 5.8.7. Open-Drain Output 5.8.8. Pull-up Resistor 5.8.9. Bus-Hold Circuitry
5.9. On-Chip I/O Termination in Arria V Devices x
5.9.1. RS OCT without Calibration in Arria® V Devices 5.9.2. RS OCT with Calibration in Arria® V Devices 5.9.3. RT OCT with Calibration in Arria® V Devices 5.9.4. Dynamic OCT in Arria® V Devices 5.9.5. LVDS Input RD OCT in Arria V Devices 5.9.6. OCT Calibration Block in Arria V Devices
5.9.6. OCT Calibration Block in Arria V Devices x
5.9.6.1. Calibration Block Locations in Arria® V Devices 5.9.6.2. Sharing an OCT Calibration Block on Multiple I/O Banks
5.9.6.2. Sharing an OCT Calibration Block on Multiple I/O Banks x
5.9.6.2.1. OCT Calibration Block Sharing Example
5.10. External I/O Termination for Arria V Devices x
5.10.1. Single-ended I/O Termination 5.10.2. Differential I/O Termination
5.10.2. Differential I/O Termination x
5.10.2.1. Differential HSTL, SSTL, and HSUL Termination 5.10.2.2. LVDS, RSDS, and Mini-LVDS Termination 5.10.2.3. Emulated LVDS, RSDS, and Mini-LVDS Termination 5.10.2.4. LVPECL Termination
6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices x
6.1. Dedicated High-Speed Circuitries in Arria® V Devices 6.2. High-Speed I/O Design Guidelines for Arria® V Devices 6.3. Differential Transmitter in Arria V Devices 6.4. Differential Receiver in Arria V Devices 6.5. Source-Synchronous Timing Budget 6.6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices Revision History
6.1. Dedicated High-Speed Circuitries in Arria® V Devices x
6.1.1. SERDES and DPA Bank Locations in Arria® V Devices 6.1.2. LVDS SERDES Circuitry 6.1.3. True LVDS Buffers in Arria® V Devices 6.1.4. Emulated LVDS Buffers in Arria V Devices
6.2. High-Speed I/O Design Guidelines for Arria® V Devices x
6.2.1. PLLs and Clocking for Arria® V Devices 6.2.2. LVDS Interface with External PLL Mode 6.2.3. Pin Placement Guidelines for DPA and Non-DPA Differential Channels
6.2.1. PLLs and Clocking for Arria® V Devices x
6.2.1.1. Guideline: Use PLLs in Integer PLL Mode for LVDS 6.2.1.2. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
6.2.2. LVDS Interface with External PLL Mode x
6.2.2.1. Altera_PLL Signal Interface with ALTLVDS IP Core 6.2.2.2. Altera_PLL Parameter Values for External PLL Mode 6.2.2.3. Connection between Altera_PLL and ALTLVDS
6.2.3. Pin Placement Guidelines for DPA and Non-DPA Differential Channels x
6.2.3.1. Guideline: Using DPA-Enabled Differential Channels 6.2.3.2. Guideline: Using DPA-Disabled Differential Channels
6.3. Differential Transmitter in Arria V Devices x
6.3.1. Transmitter Blocks 6.3.2. Transmitter Clocking 6.3.3. Serializer Bypass for DDR and SDR Operations 6.3.4. Programmable Differential Output Voltage 6.3.5. Programmable Pre-Emphasis
6.4. Differential Receiver in Arria V Devices x
6.4.1. Receiver Blocks in Arria V Devices 6.4.2. Receiver Modes in Arria V Devices 6.4.3. Receiver Clocking for Arria V Devices 6.4.4. Differential I/O Termination for Arria V Devices
6.4.1. Receiver Blocks in Arria V Devices x
6.4.1.1. DPA Block 6.4.1.2. Synchronizer 6.4.1.3. Data Realignment Block (Bit Slip) 6.4.1.4. Deserializer
6.4.2. Receiver Modes in Arria V Devices x
6.4.2.1. Non-DPA Mode 6.4.2.2. DPA Mode 6.4.2.3. Soft-CDR Mode
6.5. Source-Synchronous Timing Budget x
6.5.1. Differential Data Orientation 6.5.2. Differential I/O Bit Position 6.5.3. Transmitter Channel-to-Channel Skew 6.5.4. Receiver Skew Margin for Non-DPA Mode
6.5.2. Differential I/O Bit Position x
6.5.2.1. Differential Bit Naming Conventions
6.5.4. Receiver Skew Margin for Non-DPA Mode x
6.5.4.1. Assigning Input Delay to LVDS Receiver Using Timing Analyzer
7. External Memory Interfaces in Arria V Devices x
7.1. External Memory Performance 7.2. HPS External Memory Performance 7.3. Memory Interface Pin Support in Arria V Devices 7.4. External Memory Interface Features in Arria V Devices 7.5. Hard Memory Controller 7.6. External Memory Interfaces in Arria V Devices Revision History
7.3. Memory Interface Pin Support in Arria V Devices x
7.3.1. Guideline: Using DQ/DQS Pins 7.3.2. DQ/DQS Bus Mode Pins for Arria® V Devices 7.3.3. DQ/DQS Groups in Arria V GX 7.3.4. DQ/DQS Groups in Arria V GT 7.3.5. DQ/DQS Groups in Arria V GZ 7.3.6. DQ/DQS Groups in Arria V SX 7.3.7. DQ/DQS Groups in Arria V ST
7.4. External Memory Interface Features in Arria V Devices x
7.4.1. UniPHY IP 7.4.2. External Memory Interface Datapath 7.4.3. DQS Phase-Shift Circuitry 7.4.4. Phase Offset Control for Arria® V GZ Devices 7.4.5. PHY Clock (PHYCLK) Networks 7.4.6. DQS Logic Block 7.4.7. Leveling Circuitry for Arria V GZ Devices 7.4.8. Dynamic OCT Control 7.4.9. IOE Registers 7.4.10. Delay Chains 7.4.11. I/O and DQS Configuration Blocks
7.4.3. DQS Phase-Shift Circuitry x
7.4.3.1. Delay-Locked Loop 7.4.3.2. DLL Reference Clock Input for Arria V Devices 7.4.3.3. DLL Phase-Shift
7.4.6. DQS Logic Block x
7.4.6.1. Update Enable Circuitry 7.4.6.2. DQS Delay Chain 7.4.6.3. DQS Postamble Circuitry 7.4.6.4. Half Data Rate Block
7.4.9. IOE Registers x
7.4.9.1. Input Registers 7.4.9.2. Output Registers
7.5. Hard Memory Controller x
7.5.1. Features of the Hard Memory Controller 7.5.2. Multi-Port Front End 7.5.3. Bonding Support 7.5.4. Hard Memory Controller Width for Arria V GX 7.5.5. Hard Memory Controller Width for Arria V GT 7.5.6. Hard Memory Controller Width for Arria V SX 7.5.7. Hard Memory Controller Width for Arria V ST
8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices x
8.1. Enhanced Configuration and Configuration via Protocol 8.2. MSEL Pin Settings 8.3. Configuration Sequence 8.4. Configuration Timing Waveforms 8.5. Device Configuration Pins 8.6. Fast Passive Parallel Configuration 8.7. Active Serial Configuration 8.8. Using EPCS and EPCQ Devices 8.9. Passive Serial Configuration 8.10. JTAG Configuration 8.11. Configuration Data Compression 8.12. Remote System Upgrades 8.13. Design Security 8.14. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Revision History
8.3. Configuration Sequence x
8.3.1. Power Up 8.3.2. Reset 8.3.3. Configuration 8.3.4. Configuration Error Handling 8.3.5. Initialization 8.3.6. User Mode
8.4. Configuration Timing Waveforms x
8.4.1. FPP Configuration Timing 8.4.2. AS Configuration Timing 8.4.3. PS Configuration Timing
8.5. Device Configuration Pins x
8.5.1. I/O Standards and Drive Strength for Configuration Pins 8.5.2. Configuration Pin Options in the Quartus® Prime Software
8.6. Fast Passive Parallel Configuration x
8.6.1. Fast Passive Parallel Single-Device Configuration 8.6.2. Fast Passive Parallel Multi-Device Configuration 8.6.3. Transmitting Configuration Data
8.6.2. Fast Passive Parallel Multi-Device Configuration x
8.6.2.1. Pin Connections and Guidelines 8.6.2.2. Using Multiple Configuration Data 8.6.2.3. Using One Configuration Data
8.7. Active Serial Configuration x
8.7.1. DATA Clock (DCLK) 8.7.2. Active Serial Single-Device Configuration 8.7.3. Active Serial Multi-Device Configuration 8.7.4. Estimating the Active Serial Configuration Time
8.7.3. Active Serial Multi-Device Configuration x
8.7.3.1. Pin Connections and Guidelines 8.7.3.2. Using Multiple Configuration Data
8.8. Using EPCS and EPCQ Devices x
8.8.1. Controlling EPCS and EPCQ Devices 8.8.2. Trace Length and Loading Guideline 8.8.3. Programming EPCS and EPCQ Devices
8.8.3. Programming EPCS and EPCQ Devices x
8.8.3.1. Programming EPCS Using the JTAG Interface 8.8.3.2. Programming EPCQ Using the JTAG Interface 8.8.3.3. Programming EPCS Using the Active Serial Interface 8.8.3.4. Programming EPCQ Using the Active Serial Interface
8.9. Passive Serial Configuration x
8.9.1. Passive Serial Single-Device Configuration Using an External Host 8.9.2. Passive Serial Single-Device Configuration Using an Intel® FPGA Download Cable 8.9.3. Passive Serial Multi-Device Configuration
8.9.3. Passive Serial Multi-Device Configuration x
8.9.3.1. Pin Connections and Guidelines 8.9.3.2. Using Multiple Configuration Data 8.9.3.3. Using One Configuration Data 8.9.3.4. Using PC Host and Download Cable
8.10. JTAG Configuration x
8.10.1. JTAG Single-Device Configuration 8.10.2. JTAG Multi-Device Configuration 8.10.3. CONFIG_IO JTAG Instruction
8.10.2. JTAG Multi-Device Configuration x
8.10.2.1. Pin Connections and Guidelines 8.10.2.2. Using a Download Cable
8.11. Configuration Data Compression x
8.11.1. Enabling Compression Before Design Compilation 8.11.2. Enabling Compression After Design Compilation 8.11.3. Using Compression in Multi-Device Configuration
8.12. Remote System Upgrades x
8.12.1. Configuration Images 8.12.2. Configuration Sequence in the Remote Update Mode 8.12.3. Remote System Upgrade Circuitry 8.12.4. Enabling Remote System Upgrade Circuitry 8.12.5. Remote System Upgrade Registers 8.12.6. Remote System Upgrade State Machine 8.12.7. User Watchdog Timer
8.12.5. Remote System Upgrade Registers x
8.12.5.1. Control Register 8.12.5.2. Status Register
8.13. Design Security x
8.13.1. Unique Chip ID IP Core 8.13.2. JTAG Secure Mode 8.13.3. Security Key Types 8.13.4. Security Modes 8.13.5. Design Security Implementation Steps
9. SEU Mitigation for Arria V Devices x
9.1. Error Detection Features 9.2. Configuration Error Detection 9.3. User Mode Error Detection 9.4. Specifications 9.5. Using Error Detection Features in User Mode 9.6. SEU Mitigation for Arria V Devices Revision History
9.4. Specifications x
9.4.1. Minimum EMR Update Interval 9.4.2. Error Detection Frequency 9.4.3. CRC Calculation Time For Entire Device
9.5. Using Error Detection Features in User Mode x
9.5.1. Enabling Error Detection 9.5.2. CRC_ERROR Pin 9.5.3. Error Detection Registers 9.5.4. Error Detection Process 9.5.5. Testing the Error Detection Block
10. JTAG Boundary-Scan Testing in Arria V Devices x
10.1. BST Operation Control 10.2. I/O Voltage for JTAG Operation 10.3. Performing BST 10.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry 10.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing 10.6. IEEE Std. 1149.1 Boundary-Scan Register 10.7. IEEE Std. 1149.6 Boundary-Scan Register 10.8. JTAG Boundary-Scan Testing inArria V Devices Revision History
10.1. BST Operation Control x
10.1.1. IDCODE 10.1.2. Supported JTAG Instruction 10.1.3. JTAG Secure Mode 10.1.4. JTAG Private Instruction
10.6. IEEE Std. 1149.1 Boundary-Scan Register x
10.6.1. Boundary-Scan Cells of an Arria V Device I/O Pin
11. Power Management in Arria V Devices x
11.1. Power Consumption 11.2. Programmable Power Technology 11.3. Temperature Sensing Diode 11.4. Hot-Socketing Feature 11.5. Hot-Socketing Implementation 11.6. Arria V GX, GT, SX, and ST Power-Up Sequence 11.7. Arria V GZ Power-Up Sequence 11.8. Power-On Reset Circuitry 11.9. Power Management in Arria V Devices Revision History
11.1. Power Consumption x
11.1.1. Dynamic Power Equation
11.3. Temperature Sensing Diode x
11.3.1. Internal Temperature Sensing Diode 11.3.2. External Temperature Sensing Diode
11.8. Power-On Reset Circuitry x
11.8.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices
2. Embedded Memory Blocks in Arria V Devices
3. Variable Precision DSP Blocks in Arria V Devices
4. Clock Networks and PLLs in Arria V Devices
5. I/O Features in Arria V Devices
6. High-Speed Differential I/O Interfaces and DPA in Arria® V Devices
7. External Memory Interfaces in Arria V Devices
8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices
9. SEU Mitigation for Arria V Devices
10. JTAG Boundary-Scan Testing in Arria V Devices
11. Power Management in Arria V Devices

7.5.1. Features of the Hard Memory Controller

Table 87.  Features of the Arria V Hard Memory Controller

Feature

Description

Memory Interface Data Width

  • 8, 16, and 32 bit data
  • 16 bit data + 8 bit ECC
  • 32 bit data + 8bit ECC

Memory Density

The controller supports up to four gigabits density parts and two chip selects.

Memory Burst Length

  • DDR3—Burst length of 8 and burst chop of 4
  • DDR2—Burst lengths of 4 and 8

Command and Data Reordering

The controller increases efficiency through the support for out-of-order execution of DRAM commands—with address collision detection-and in-order return of results.

Starvation Control

A starvation counter ensures that all requests are served after a predefined time-out period. This function ensures that data with low priority access are not left behind when reordering data for efficiency.

User-Configurable Priority Support

When the controller detects a high priority request, it allows the request to bypass the current queuing request. This request is processed immediately and thus reduces latency.

Avalon®-MM Data Slave Local Interface

By default, the controller supports the Avalon Memory-Mapped protocol.

Bank Management

By default, the controller provides closed-page bank management on every access. The controller intelligently keeps a row open based on incoming traffic. This feature improves the efficiency of the controller especially for random traffic.

Streaming Reads and Writes

The controller can issue reads or writes continuously to sequential addresses every clock cycle if the bank is open. This function allows for very high efficiencies with large amounts of data.

Bank Interleaving

The controller can issue reads or writes continuously to 'random' addresses.

Predictive Bank Management

The controller can issue bank management commands early so that the correct row is open when the read or write occurs. This increases efficiency.

Multiport Interface

The interface allows you to connect up to six data masters to access the memory controller through the local interface. You can update the multiport scheduling configuration without interrupting traffic on a port.

Built-in Burst Adaptor

The controller can accept bursts of arbitrary sizes on its local interface and map these bursts to efficient memory commands.

Run-time Configuration of the Controller

This feature provides support for updates to the timing parameters without requiring reconfiguration of the FPGA, apart from the standard compile-time setting of the timing parameters.

On-Die Termination

The controller controls the on-die termination (ODT) in the memory, which improves signal integrity and simplifies your board design.

User-Controlled Refresh Timing

You can optionally control when refreshes occur—allowing the refreshes to avoid clashing of important reads or writes with the refresh lock-out time.

Low Power Modes

You can optionally request the controller to put the memory into the self-refresh or deep power-down modes.

Partial Array Self-Refresh

You can select the region of memory to refresh during self-refresh through the mode register to save power.

ECC

Standard Hamming single error correction, double error detection (SECDED) error correction code (ECC) support:

  • 32 bit data + 8 bit ECC
  • 16 bit data + 8 bit ECC

Additive Latency

With additive latency, the controller can issue a READ/WRITE command after the ACTIVATE command to the bank prior to t RCD to increase the command efficiency.

CAUTION:
Efficiency degradation may occur when using the additive latency feature with the hard memory controller for DDR3 SDRAM interfaces at 533 MHz.

Write Acknowledgment

The controller supports write acknowledgment on the local interface.

User Control of Memory Controller Initialization

The controller supports initialization of the memory controller under the control of user logic—for example, through the software control in the user system if a processor is present.

Controller Bonding Support

You can bond two controllers to achieve wider data width for higher bandwidth applications.

Level Two Title