Arria® V Device Handbook: Volume 1: Device Interfaces and Integration
Visible to Intel only — GUID: sam1403479949868
Ixiasoft
Visible to Intel only — GUID: sam1403479949868
Ixiasoft
8.1. Enhanced Configuration and Configuration via Protocol
Mode | Data Width | Max Clock Rate (MHz) | Max Data Rate (Mbps) | Decompression | Design Security | Remote System Update |
---|---|---|---|---|---|---|
AS through the EPCS and EPCQ serial configuration device | 1 bit, 4 bits | 100 | — | Yes | Yes | Yes |
PS through CPLD or external microcontroller | 1 bit | 125 | 125 | Yes | Yes | — |
FPP | 8 bits | 125 | — | Yes | Yes | Parallel flash loader |
16 bits | 125 | — | Yes | Yes | ||
32 bits26 | 100 | — | Yes | Yes | ||
CvP (PCIe) | x1, x2, x4, and x8 lanes | — | — | Yes | Yes | — |
JTAG | 1 bit | 33 | 33 | — | — | — |
Configuration via HPS | 16 bits | 125 | — | Yes | Yes | Parallel flash loader |
32 bits | 100 | — | Yes | Yes |
Instead of using an external flash or ROM, you can configure the Arria® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Arria® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.