Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab Board Information System-MAX Control JTAG Chain Platform Designer (Standard) Memory Map 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

6.3.2. The System Info Tab

The System Info tab shows information about the board's current configuration. The tab displays system- MAX® V control setting, the board's MAC address, and other details stored on the board.

Figure 17. The System Info Tab

The following sections describe the controls on the System Info tab.

Board Information

The Board Information control displays static information about your board.
  • Board Name: Indicates the official name of the board given by the BTS.
  • Board P/N: Indicates the part number of the board.
  • Serial Number: Indicates the serial number of the board.
  • Board Revision: Indicates the revision of the board.
  • MAC: Indicates the MAC address of the board.

System-MAX Control

The MAX® V register control allows you to view and change the current MAX® V register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 26.  MAX V Registers
MAX V Register Values Description
Configure Resets the system and reloads the FPGA with a design from flash memory based on the other MAX® V register values.
PSO Sets the MAX® V PSO register
PSR Sets the MAX® V PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corrresponds to the page of flash memory to load during the FPGA reconfiguration.
PSS Displays the MAX® V PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.
MAX Ver Indicates the version of MAX® V code currently running on the board.The MAX® V code resides in the <package dir>\examples\max5 directory. Newer revisions of this code may be available on the Stratix 10 Transceiver Signal Integrity Development Kit link on the Intel® website.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain.
Note: When switch SW 3-2 (MAX BYPASS) is set to 1, the JTAG chain includes the MAX® V device. When set to 0, the MAX® V device is removed from the JTAG chain. System MAX and FPGA should all be in the JTAG chain when running the BTS GUI.

Platform Designer (Standard) Memory Map

The Platform Designer (Standard) memory map control shows the memory map of bts_config.sof design running on your board. This can be visible when bts_config.sof design is running on board.

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