Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

Download PDF
ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.5. Status Elements

The development board includes board-specific status LEDs and switches for enabling and configuring various features on the board, as well as 16 character x 2 line LCD for displaying board power and temperature measurements. This section describes these status elements.

Table 9.  Board Specific LEDs
Board Reference Signal Name Description
D29 --- Green LED. Power 3.3V present.
D31 --- Green LED. Power 3.3V PRE present.
D32 --- Green LED. Power 12V present.
D5 FAPRSNT_N Green LED. FMC A daughter card present.
D6 FBPRSNT_N Green LED. FMC B daughter card present.
D36 ERR_LED_N Amber LED. System Power error indicator.
D1 JTAG_RX Green LED. JTAG receiver activity indicator.
D2 JTAG_TX Green LED. JTAG transmitter activity indicator.
D3 SC_RX Green LED. System console receiver activity indicator.
D4 SC_TX Green LED. System console transmittter activity indicator.
D7 ENET_LED_TX Green LED. Blinks to indicate Ethernet PHY transmit activity.
D8 ENET_LED_RX Green LED. Blinks to indicate Ethernet PHY activity.
D9 ENET_LED_LINK1000 Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed.
D10 ENET_LED_LINK100 Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed.
D11 ENET_LED_LINK10 Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed.
D27 OVERTEMPn Amber LED. Intel® Stratix® 10 over temperature indicator.
Level Two Title