Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.4.3. FPGA Programming over External Intel® FPGA Download Cable II

The JTAG chain allows programming of both the Intel® Stratix® 10 GX FPGA and MAX® V CPLD devices using an external Intel® FPGA Download Cable II dongle or the on-board Intel® FPGA Download Cable II via the USB Interface Connector.

During board bring-up, and as a back-up in case the on-board Intel® FPGA Download Cable II has a problem, the external Intel® FPGA Download Cable II dongle can be used to program both the Intel® Stratix® 10 and MAX® V CPLD via the Intel® FPGA Download Cable II 2x5 pin 0.1" programming header (J14)

Another 2x5 pin 0.1" vertical non-shrouded header (J15) is provided on the board for programming the Intel® MAX® 10 FPGA for configuring the Intel® FPGA Download Cable II circuitry. Once the Intel® FPGA Download Cable II is configured and operational, the Intel® FPGA Download Cable II can be used for subsequent programming of the Intel® Stratix® 10 GX FPGA and MAX® V CPLD.

The Intel® FPGA Download Cable II JTAG chain connects four JTAG nodes in the following order, with the option to bypass the Intel® Stratix® 10, MAX® V, FMC A or FMC B by a dip switch SW3 setting as follows:
  • Switch closed/ON: Corresponding JTAG node is bypassed.
  • Switch open/OFF: Corresponding JTAG node is enabled in the JTAG chain.

Pin 2 of the J14 Header is used to disable the embedded Intel® FPGA Download Cable II by connecting it to the embedded Intel® FPGA Download Cable IIs low active disable pin with a pull-up resistor. Since Pin 2 from the mating Intel® FPGA Download Cable II dongle is GND, when the dongle is connected into the JTAG header, the embedded Intel® FPGA Download Cable II is disabled to avoid contention with the external Intel® FPGA Download Cable II dongle.

Figure 7. JTAG Chain
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