Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.4.2. FPGA Programming from Flash Memory

The figure below shows a detailed schematic block diagram for the MAX V + Flash AvSTx32 mode configuration implementation.

Note: Typical JTAG clock frequency for CFI Flash programming via PFL II core is 16 MHz. You may try it with a lower frequency such as 6 MHz if it fails with 16 MHz.
Figure 6. MAX V + Flash AvSTx32 Configuration Block Diagram

Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its Flash interface signals to avoid contention with the FPGA. The PGMSEL dipswitch (S10) is provided to select between two POF files (FACTORY and USER) stored on the Flash.

The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx32 configuration in the MAX® V CPLD. The PFL II Megafunction reads data from the flash and converts it to AvST format. This data is written into the Intel® Stratix® 10 GX FPGA device through dedicated AvST CLK and FPGA Config Data [31:0] pins at corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.

Implementation will be done using an Intel® MAX® V 5M2210ZF256FBGA CPLD acting as the AvST download controller and two 1G Flash devices. The Flash will be Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX® V CPLD shares the CFI Flash interface with the Intel® Stratix® 10 GX FPGA. No arbitration is needed between MAX® V CPLD and Intel® Stratix® 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization.

After a POWER-ON or RESET (reconfiguration) event, the MAX® V device shall configure the Intel® Stratix® 10 GX FPGA in the AvSTx32 mode with either the FACTORY POF or an USER DEFINED POF depnding on the FACTORY_LOAD setting.

The MSEL[2:0] pins indicate which configuration scheme is chosen. The manufacturing default condition is [000] for AvSTx32 scheme.

For different configuration modes, MSEL [2:0] signals must be set acccording to the table below:
Table 8.  Support Configuration Modes for Stratix 10 Transceiver Signal Integrity Development Kit
Configuration Scheme MSEL [2:0]
Avalon-ST (x32) 000
Avalon-ST (x16) 101
AS (Normal mode) 011
JTAG only 111
Not supported Other Settings
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