Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab Status Port PMA Setting Data Type Error Control Run Control 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

6.3.5. The FMCA Tab

This tab allows you to perform loopback tests on the FMCA port.

Figure 20. The FMCA tab

The following sections describe the controls on the FMCA tab.

Status

Displays the following status information during a loopback test:
  • PLL Lock: Shows the PLL locked or unlocked state.
  • Pattern Sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
  • Details: Shows the PLL lock and pattern status:

Port

Allows you to specify which interface to test. The following port tests are available: XCVR and CMOS

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
    • 2nd pre (L-Tile): Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • 1st post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
    • 2nd post (L-Tile): Specifies the amount of pre-emphasis on the second post-tap of the transmitter buffer.
  • Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage mode.
  • DC gain: Specifies the DC gain setting for the receiver equalizer in four stage mode.
  • VGA: Specifies the VGA gain value.

Data Type

Specifies the type of data contained in the transactions. The following data types are available for analysis.
  • PRBS 7: Selects pseudo-random 7-bit sequences.
  • PRBS 15: Selects pseudo-random 15-bit sequences.
  • PRBS 23: Selects pseudo-random 23-bit sequences.
  • PRBS 31: Selects pseudo-random 31-bit sequences.
  • HF: Selects highest frequency divide-by-2 data pattern 10101010.
  • LF: Selects lowest frequency divide-by-33 data pattern.

Error Control

Displays data errors detected during analysis and allows you to insert errors:
  • Detected errors: Displays the number of data errors detected in the hardware.
  • Inserted errors: Displays the number of errors inserted into the transmit data stream.
  • Insert: Inserts a one-word error into the transmit data stream each time you click the button. Insert is enabled only during transaction performance analysis.
  • Clear: Resets the Detected errors and Inserted errors counters to zeroes.

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This control initiates the loopback tests.

Data Rate (H-Tile): Displays the XCVR type and data rate of each channel.
Figure 21. FMCA Data Rate

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

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