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1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
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4.2.3. UFM Program (Write) Operation
The UFM offers a single 32-bit program (write) operation.
To perform a UFM program operation, follow these steps:
- Disable the write protection mode. Write 0 into the write protection register for the sector of the given data through the Avalon-MM control interface.
- Program the following data into flash through the Avalon-MM data interface.
- Address: legal address (from Avalon-MM address map)
- Data: user data
Set burst count to 1 (parallel mode) or 32 (serial mode).
- The flash IP core sets the busy field in the status register to 2'b10 when the program operation is in progress.
- If the operation goes well, the flash IP core sets the write successful field in the status register to 1'b1 or write successful. The flash IP core sets the write successful field in the status register to 1'b0 (failed) if one of the following conditions takes place:
- The burst count is not equal to 1 (parallel mode) or 32 (serial mode).
- The given address is out of range.
- The sector protection mode or write protection mode of the corresponding sector is not clear (the value is not 1'b0).
- Repeat the earlier steps if you want to perform another program operation.
- You have to enable back the write protection mode when the program operation completes. Write 1 into the write protection register for the corresponding sector through the Avalon-MM control interface.
Note: Check the status register after each write to make sure the program operation is successful (write successful).
Figure 8. Program Operation in Parallel ModeThe figure below shows the write data timing diagram in parallel mode.
Figure 9. Program Operation in Serial ModeThe figure below shows the write data timing diagram in serial mode.