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1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
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4.2.7.1. UFM Data Incrementing Burst Read
The following figures show the timing diagrams for the data incrementing burst read operations for the different Intel® MAX® 10 devices.
Figure 13. Incrementing Burst Read Operation for 10M02, 10M04, and 10M08 Devices in Parallel Mode
Figure 14. Incrementing Burst Read Operation for 10M16 and 10M25 Devices in Parallel Mode
Figure 15. Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode
Figure 16. Unaligned Address Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode
Figure 17. Incrementing Burst Read Operation for Intel® MAX® 10 Devices in Serial Mode