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1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
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2.2. UFM Memory Organization Map
The address scheme changes based on the configuration mode you specify in the On-Chip Flash Intel® FPGA IP core parameter editor.
The following tables show the dynamic UFM support based on different configuration mode and Intel® MAX® 10 variant.
Configuration | UFM1 | UFM0 | CFM2 (Image 2) |
CFM1 (Image 2) |
CFM0 (Image 1) |
---|---|---|---|---|---|
Dual compressed images | UFM space | UFM space | — | — | — |
Single uncompressed image | UFM space | UFM space | UFM space | — | — |
Single compressed image | UFM space | UFM space | UFM space | UFM space | — |
Single uncompressed image with memory initialization | UFM space | UFM space | — | — | — |
Single compressed image with memory initialization | UFM space | UFM space | — | — | — |
Configuration | UFM1 | UFM0 | CFM2 (Image 2) |
CFM1 (Image 2) |
CFM0 (Image 1) |
---|---|---|---|---|---|
Dual compressed images | Not available | ||||
Single uncompressed image | UFM space | UFM space | — | — | — |
Single compressed image | UFM space | UFM space | — | — | — |
Single uncompressed image with memory initialization | Not available | ||||
Single compressed image with memory initialization | Not available |