Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

2.1. UFM and CFM Array Size

Each array is organized as various sectors.

A page is the smallest amount of flash memory that you can erase at one time. A sector contains a number of pages. You can erase each page or sector independently.

The On-Chip Flash Intel® FPGA IP core also gives you access to configuration flash memory (CFM) based on your specification in the parameter editor.

Table 1.  UFM and CFM Array SizeThis table lists the dimensions of the UFM and CFM arrays.
Device Pages per Sector Page Size (Kb) Total User Flash Memory Size (Kb) 1 Total Configuration Memory Size (Kb) 1
UFM1 UFM0 CFM2

(Image 2)

 CFM1

(Image 2)

 CFM0

(Image 1)
10M02/

10M02SCU324 		3 3 0/0 0/29 34/70 16/16 96/96 544/1584
10M04 0 8 41 29 70 16 1,248 2,240
10M08 8 8 41 29 70 16 1,376 2,240
10M16 4 4 38 28 66 32 2,368 4,224
10M25 4 4 52 40 92 32 3,200 5,888
10M40 4 4 48 36 84 64 5,888 10,752
10M50 4 4 48 36 84 64 5,888 10,752
1 The maximum possible value, which is dependent on the mode you select.
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