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1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
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4.2.7.2. UFM Data Wrapping Burst Read
The UFM supports data wrapping when it receives an unaligned address.
Note: Wrapping burst read is available only for parallel interface.
Device | Data Register Length | Flash IP Data Bus Width | Fixed Supported Burst Count | Data Wrapping |
---|---|---|---|---|
10M02SCU324, 10M04, or 10M08 | 32 | 64 | 2 | The address wraps back to the previous boundary after 64 bits or 2 cycles. For example, for a wrapping in a 32-bit data interface:
|
10M16, 10M25, 10M40, or 10M50 | 32 | 128 | 4 | The address wraps back to the previous boundary after 128 bits or 4 cycles. For example, for a wrapping in a 32-bit data interface:
|
The following figures show the timing diagrams for the data wrapping burst read operations for the different Intel® MAX® 10 devices.
Figure 18. Wrapping Burst Read Operation for 10M04 and 10M08 Devices