Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

5.1. On-Chip Flash Intel® FPGA IP Core Parameters

The following table lists the parameters for the On-Chip Flash Intel® FPGA IP core.
Table 8.  On-Chip Flash Intel® FPGA IP Core Parameters
Parameters Default Value Description
Data interface Parallel Allows you to select the type of interface. You can choose parallel or serial.
Read burst mode Incrementing
Allows you to select the type of read burst mode. You can choose incrementing or wrapping.
Incrementing mode Read burst count is 2, 4, 8, ... 128
Wrapping mode Burst count fixed to 2 or 4
Note: Serial interface supports only incrementing mode. Parallel interface does not support wrapping mode for 10M02 devices.
Read burst count 2 Allows you the flexibility to adjust the maximum burst count bus width.
  • Parallel mode: This setting represents the maximum burst count number.
  • Serial mode: This setting supports stream read and represents the words to be read for each read operation. The Avalon-MM interface burst count bus width is equal to 32*read burst count.
Configuration mode Single uncompressed image Allows you to select the configuration mode. You can choose one of these options:
  • Dual compressed images
  • Single uncompressed image: Accesses CFM2 sector as UFM
  • Single compressed image: Accesses CFM2 and CFM1 sectors as UFM
  • Single uncompressed image with memory initialization
  • Single compressed image with memory initialization
Flash Memory —

The sector ID, address range value, and flash type are generated dynamically by hardware .tcl based on the device and configuration mode you select. Indicates the address mapping for each sector and adjusts the Access Mode for each sector individually.

Note: Only CFM sectors support Hidden access mode.
Clock frequency 116.0 MHz Key in the appropriate clock frequency in MHz. The maximum frequency is 116.0 MHz for parallel interface and 7.25 MHz for serial interface.
Note: If you use 10M02 devices, the maximum frequency for parallel interface is 7.25 MHz.
Initialize flash content Off Turn on this option to initialize the flash content.
Enable non-default initialization file Off Turn on this option to enable your preferred initialization file. If you choose to have a non-default file, type the filename or select the .hex or .mif file using the browse button.
User created hex or mif file — This option is only available if you turn on Enable non-default initialization file. Assign your own .hex or .mif filename.
User created dat file for simulation — This option is only available if you turn on Enable non-default initialization file. Assign your own simulation filename.
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