Visible to Intel only — GUID: vgo1397656193368
Ixiasoft
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
Visible to Intel only — GUID: vgo1397656193368
Ixiasoft
4.1. On-Chip Flash Intel® FPGA IP Core
The IP core design flow helps you get started with any IP core.
The On-Chip Flash Intel® FPGA IP core is installed as part of the Intel® Quartus® Prime installation process. You can select and parameterize any IP core from the Intel FPGA IP library. Intel provides an integrated parameter editor that allows you to customize the On-Chip Flash Intel® FPGA IP core to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports.
Related Information