Intel® MAX® 10 User Flash Memory User Guide

ID 683180
Date 8/30/2022
Public
Document Table of Contents

2.3. UFM Block Diagrams

This figure shows the top level view of the On-Chip Flash Intel® FPGA IP core block diagram. The On-Chip Flash Intel® FPGA IP core supports both parallel and serial interfaces for Intel® MAX® 10 FPGAs.

Figure 1. On-Chip Flash Intel® FPGA IP Core Block Diagram
This IP block has two Avalon-MM slave controllers:
  • Data—a wrapper of the UFM block that provides read and program accesses to the flash.
  • Control—the CSR and status register for the flash, which is required only for program and erase operations.

These figures show the detailed overview of the Avalon-MM interface during read and program (write) operation.

Figure 2. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Parallel ModeThis figure shows the standard interface for Intel® MAX® 10 devices in parallel mode.
Note: The maximum frequency for all devices in parallel mode, except for 10M02 2, is 116 MHz. The maximum frequency for 10M022 devices is 7.25 MHz.
Figure 3. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Serial ModeThis figure shows the standard interface for Intel® MAX® 10 devices in serial mode.

These figures show the detailed overview of the Avalon-MM interface during read only operation.

Figure 4. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Parallel Mode
Figure 5. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Serial Mode
2 10M02 does not include 10M02SCU324.