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1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
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2.3. UFM Block Diagrams
This figure shows the top level view of the On-Chip Flash Intel® FPGA IP core block diagram. The On-Chip Flash Intel® FPGA IP core supports both parallel and serial interfaces for Intel® MAX® 10 FPGAs.
Figure 1. On-Chip Flash Intel® FPGA IP Core Block Diagram
This IP block has two Avalon-MM slave controllers:
- Data—a wrapper of the UFM block that provides read and program accesses to the flash.
- Control—the CSR and status register for the flash, which is required only for program and erase operations.
These figures show the detailed overview of the Avalon-MM interface during read and program (write) operation.
Figure 2. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Parallel ModeThis figure shows the standard interface for Intel® MAX® 10 devices in parallel mode.
Figure 3. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Serial ModeThis figure shows the standard interface for Intel® MAX® 10 devices in serial mode.
These figures show the detailed overview of the Avalon-MM interface during read only operation.
Figure 4. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Parallel Mode
Figure 5. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Serial Mode
2 10M02 does not include 10M02SCU324.