Intel® MAX® 10 User Flash Memory User Guide

ID 683180
Date 8/30/2022
Public
Document Table of Contents

5.2. On-Chip Flash Intel® FPGA IP Core Signals

The following table lists the signals for the On-Chip Flash Intel® FPGA IP core.
Table 9.  Avalon-MM Slave Input and Output Signals for Parallel and Serial Modes.
Signal Width Direction Description
Clock and Reset
clock 1 Input System clock signal that clocks the entire peripheral.
reset_n 1 Input System synchronous reset signal that resets the entire peripheral. The IP core asserts this signal asynchronously. This signal becomes synchronous in the IP core after the rising edge of the clock.
Control
avmm_csr_addr 1 Input Avalon-MM address bus that decodes registers.
avmm_csr_read 1 Input Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required.
avmm_csr_readdata 32 Output Avalon-MM read back data signal. The IP core asserts this signal during read cycles.
avmm_csr_write 1 Input Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required.
avmm_csr_writedata 32 Input Avalon-MM write data bus. The bus master asserts this bus during write cycles.
Data
avmm_data_addr User-defined Input Avalon-MM address bus that indicates the flash data address. The width of this address depends on your selection of device and configuration mode.
avmm_data_read 1 Input Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required.
avmm_data_readdata
  • Parallel mode: 32
  • Serial mode: 1
Output Avalon-MM read back data signal. The IP core asserts this signal during read cycles.
avmm_data_write 1 Input Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required.
avmm_data_writedata
  • Parallel mode: 32
  • Serial mode: 1
Input Avalon-MM write data bus. The bus master asserts this bus during write cycles.
avmm_data_waitrequest 1 Output The IP core asserts this bus to pause the master when the IP core is busy during read or write operations.
avmm_data_readdatavalid 1 Output The IP core asserts this signal when the readdata signal is valid during read cycles.
avmm_data_burstcount User-defined Input The bus master asserts this signal to initiate a burst read operation.
  • In write operations, the burst count is always fixed to 1 for parallel mode and 32 for serial mode.
  • In incrementing burst read mode, the supported read burst count range:
    Parallel mode 1-2(burstcount width-1)
    Serial mode 1-128*32
  • In wrapping burst read mode (parallel mode only), the supported read burst count is fixed to 2 and 4.
    10M04, and 10M08 1–2
    10M16, 10M25, 10M40 and 10M50 1–4