5.2. On-Chip Flash Intel® FPGA IP Core Signals
The following table lists the signals for the On-Chip Flash Intel® FPGA IP core.
Signal | Width | Direction | Description | ||||||||
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Clock and Reset | |||||||||||
clock | 1 | Input | System clock signal that clocks the entire peripheral. | ||||||||
reset_n | 1 | Input | System synchronous reset signal that resets the entire peripheral. The IP core asserts this signal asynchronously. This signal becomes synchronous in the IP core after the rising edge of the clock. | ||||||||
Control | |||||||||||
avmm_csr_addr | 1 | Input | Avalon-MM address bus that decodes registers. | ||||||||
avmm_csr_read | 1 | Input | Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required. | ||||||||
avmm_csr_readdata | 32 | Output | Avalon-MM read back data signal. The IP core asserts this signal during read cycles. | ||||||||
avmm_csr_write | 1 | Input | Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required. | ||||||||
avmm_csr_writedata | 32 | Input | Avalon-MM write data bus. The bus master asserts this bus during write cycles. | ||||||||
Data | |||||||||||
avmm_data_addr | User-defined | Input | Avalon-MM address bus that indicates the flash data address. The width of this address depends on your selection of device and configuration mode. | ||||||||
avmm_data_read | 1 | Input | Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required. | ||||||||
avmm_data_readdata |
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Output | Avalon-MM read back data signal. The IP core asserts this signal during read cycles. | ||||||||
avmm_data_write | 1 | Input | Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required. | ||||||||
avmm_data_writedata |
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Input | Avalon-MM write data bus. The bus master asserts this bus during write cycles. | ||||||||
avmm_data_waitrequest | 1 | Output | The IP core asserts this bus to pause the master when the IP core is busy during read or write operations. | ||||||||
avmm_data_readdatavalid | 1 | Output | The IP core asserts this signal when the readdata signal is valid during read cycles. | ||||||||
avmm_data_burstcount | User-defined | Input | The bus master asserts this signal to initiate a burst read operation.
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