5.1. On-Chip Flash Intel® FPGA IP Core Parameters
The following table lists the parameters for the On-Chip Flash Intel® FPGA IP core.
Parameters | Default Value | Description | ||||
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Data interface | Parallel | Allows you to select the type of interface. You can choose parallel or serial. | ||||
Read burst mode | Incrementing |
Allows you to select the type of read burst mode. You can choose incrementing or wrapping.
Note: Serial interface supports only incrementing mode. Parallel interface does not support wrapping mode for 10M02 devices.
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Read burst count | 2 | Allows you the flexibility to adjust the maximum burst count bus width.
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Configuration mode | Single uncompressed image | Allows you to select the configuration mode. You can choose one of these options:
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Flash Memory | — | The sector ID, address range value, and flash type are generated dynamically by hardware .tcl based on the device and configuration mode you select. Indicates the address mapping for each sector and adjusts the Access Mode for each sector individually.
Note: Only CFM sectors support Hidden access mode.
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Clock frequency | 116.0 MHz | Key in the appropriate clock frequency in MHz. The maximum frequency is 116.0 MHz for parallel interface and 7.25 MHz for serial interface.
Note: If you use 10M02 devices, the maximum frequency for parallel interface is 7.25 MHz.
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Initialize flash content | Off | Turn on this option to initialize the flash content. | ||||
Enable non-default initialization file | Off | Turn on this option to enable your preferred initialization file. If you choose to have a non-default file, type the filename or select the .hex or .mif file using the browse button. | ||||
User created hex or mif file | — | This option is only available if you turn on Enable non-default initialization file. Assign your own .hex or .mif filename. | ||||
User created dat file for simulation | — | This option is only available if you turn on Enable non-default initialization file. Assign your own simulation filename. |