Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

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ID 683175
Date 12/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices 2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices 3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices 5. Factors Affecting the Accuracy of the Early Power Estimator 6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices x
1.1. Intel® Stratix® 10 EPE Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices 2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator
2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface x
3.1. Intel® Stratix® 10 EPE Input Fields 3.2. Intel® Stratix® 10 EPE Output Fields 3.3. Intel® Stratix® 10 EPE Input/Output Fields 3.4. Intel® Stratix® 10 EPE Field Shading 3.5. Intel® Stratix® 10 EPE Input Field Dependencies 3.6. Intel® Stratix® 10 EPE Buttons
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices x
4.1. Intel® Stratix® 10 EPE - Common Worksheet Elements 4.2. Intel® Stratix® 10 EPE - Main Worksheet 4.3. Intel® Stratix® 10 EPE - Logic Worksheet 4.4. Intel® Stratix® 10 EPE - RAM Worksheet 4.5. Intel® Stratix® 10 EPE - DSP Worksheet 4.6. Intel® Stratix® 10 EPE - Clock Worksheet 4.7. Intel® Stratix® 10 EPE - PLL Worksheet 4.8. Intel® Stratix® 10 EPE - I/O Worksheet 4.9. Intel® Stratix® 10 EPE - I/O-IP Worksheet 4.10. Intel® Stratix® 10 EPE - XCVR Worksheet 4.11. Intel® Stratix® 10 EPE - HPS Worksheet 4.12. Intel® Stratix® 10 EPE - HBM Worksheet 4.13. Intel® Stratix® 10 EPE - Thermal Worksheet 4.14. Intel® Stratix® 10 EPE - Report Worksheet 4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator x
5.1. Toggle Rate 5.2. Temperature
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices
5. Factors Affecting the Accuracy of the Early Power Estimator
6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
A. Measuring Static Power

4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet

Each row in the Regulator Selection table of the Intel® Enpirion® worksheet of the Early Power Estimator for Intel® Stratix® 10 devices represents the power solution for a single regulator group.

Intel® Enpirion® power devices are available that satisfy the power requirements for the power rails on FPGA devices. Power devices are selected based on load current, input and output voltages, and power-delivery configuration.

Regulator groups are created by combining rails that can be allowably supplied from the same source. Intel® Enpirion® device selection is enabled when Power Characteristics in the Main worksheet is set to Maximum, and the Regulator Group section of the Report worksheet is set up correctly with no grouping errors.

In the following figure, a 12-V off-line regulator supplies input power for Groups 5 and 6. The regulator for Group 6 is an intermediate supply, which does not directly power any of the FPGA supplies, but provides input power to regulators for Groups 2, 3, and 4. The 3-V regulator supplying Group 5 provides power for FPGA supplies, but also acts as an intermediate supply providing input power for Group 1.

Figure 23.  Intel® Enpirion® Worksheet of the EPE Spreadsheet for Intel® Stratix® 10 Devices
Table 26.   Intel® Enpirion® Worksheet Information
Column Heading Description
Group The regulator group number for this regulator. The regulator group numbers correspond to the group numbers shown in the Report worksheet.
Intermediate Supply Indicate whether the supply is an intermediate supply. An intermediate supply is driven by a regulator that is not connected to any supply rails on the FPGA. Instead, such a regulator drives other regulators. If a regulator provides power to both the FPGA and other regulators, this field should be set to No.
Regulator Input Voltage (V) Specifies the input voltage for the regulator. The input voltage must be higher than the output voltage. If this regulator has a parent, its input voltage is automatically set to the parent's output voltage.
Regulator Current Draw (A) Specifies the required input current to the regulator. It is assumed that all regulators have a current efficiency of 85%.
Voltage (V) Specifies the output voltage of the regulator. The voltage equals the voltage of the supply rail connected to this regulator.
Load Current (A) Specifies the load current required by the pins from the regulator. This current equals the sum of all the supply currents that are connected to this regulator, multiplied by (1 + Load Current Margin).

In addition, if this regulator is a parent of other regulators, the Load Current also includes the sum of all the children's input currents.

Load Current Margin Margin added to the load current to account for component variability.
Parent Group The group number of the regulator that supplies input voltage to the regulator in the current row. This value is applicable only when the input voltage is provided by another regulator on this worksheet.
Regulator Type Choose the type of the regulator.
POK Select Yes to select a regulator with a Power OK (POK) output to assist with sequencing.
Suggested Enpirion Part Specifies suggested Intel® Enpirion® parts to implement regulator for a given row, which meet the voltage and current requirements for this row. To finalize regulator selection, evaluate VRM voltage ripple specification and efficiency against the FPGA device requirement from the appropriate data sheets.
Pin Compatible Parts Pin compatible parts are devices with equivalent or higher current capabilities that can be placed on the same PCB footprint as the suggested Intel® Enpirion® part. Additional components or changes to component values may be required when using a pin compatible part.
Note A note may be displayed here, depending on the value chosen under Suggested Enpirion Part.
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