Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

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ID 683175
Date 12/03/2021
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Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices 2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices 3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices 5. Factors Affecting the Accuracy of the Early Power Estimator 6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices x
1.1. Intel® Stratix® 10 EPE Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices 2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator
2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface x
3.1. Intel® Stratix® 10 EPE Input Fields 3.2. Intel® Stratix® 10 EPE Output Fields 3.3. Intel® Stratix® 10 EPE Input/Output Fields 3.4. Intel® Stratix® 10 EPE Field Shading 3.5. Intel® Stratix® 10 EPE Input Field Dependencies 3.6. Intel® Stratix® 10 EPE Buttons
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices x
4.1. Intel® Stratix® 10 EPE - Common Worksheet Elements 4.2. Intel® Stratix® 10 EPE - Main Worksheet 4.3. Intel® Stratix® 10 EPE - Logic Worksheet 4.4. Intel® Stratix® 10 EPE - RAM Worksheet 4.5. Intel® Stratix® 10 EPE - DSP Worksheet 4.6. Intel® Stratix® 10 EPE - Clock Worksheet 4.7. Intel® Stratix® 10 EPE - PLL Worksheet 4.8. Intel® Stratix® 10 EPE - I/O Worksheet 4.9. Intel® Stratix® 10 EPE - I/O-IP Worksheet 4.10. Intel® Stratix® 10 EPE - XCVR Worksheet 4.11. Intel® Stratix® 10 EPE - HPS Worksheet 4.12. Intel® Stratix® 10 EPE - HBM Worksheet 4.13. Intel® Stratix® 10 EPE - Thermal Worksheet 4.14. Intel® Stratix® 10 EPE - Report Worksheet 4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator x
5.1. Toggle Rate 5.2. Temperature
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices
5. Factors Affecting the Accuracy of the Early Power Estimator
6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
A. Measuring Static Power

4.2. Intel® Stratix® 10 EPE - Main Worksheet

The Main worksheet of the Early Power Estimator (EPE) for Intel® Stratix® 10 devices allows you to enter device, package, and cooling information, and displays thermal power and thermal analysis information.
Figure 7.  Intel® Stratix® 10 EPE Main Worksheet

The required parameters depend on whether the junction temperature is manually entered or auto computed.

Table 3.  Input Parameter Information
Parameter Description
Family Select the device family.
Device

Select your device.

Larger devices consume more static power and have higher clock dynamic power. All other power components are unaffected by device selection.

Device Grade

Select the combination of Operating Temperature, Speed Grade, and Power Option used.

  • Operating Temperature: Extended (TJ = 0C to 100C), Industrial (TJ = -40C to 100C)
  • FPGA Core Fabric Speed Grade: 1 (fastest), 2 or 3.
  • Power Option: X (Extreme Low), L (Low), or V (SmartVID)
Package

Select the device package.

Larger packages provide a larger cooling surface and more contact points to the circuit board, thus they offer lower thermal resistance. Package selection does not affect dynamic power directly.

Transceiver Grade Select the transceiver grade.
Note: For information on transceiver grades, refer to Intel® Stratix® 10 Device Variants and Packages, in the Intel® Stratix® 10 Device Overview.
Power Characteristics

Select typical or theoretical worst-case silicon process.

There is a process variation from die-to-die. This variation primarily affects static power consumption.

If you choose Typical power characteristics, estimates are based on long-term projections of average power consumed by typical silicon. For FPGA board power supply design and thermal design, choose Maximum for worst-case values.

VCC Voltage (mV) Select the voltage of the VCC power rail, in mV.
Power Model Status Indicates whether the power model for the device is in preliminary, advance, or final status.

Thermal power is the power dissipated in the device. Total thermal power is the sum of the thermal power of all the resources used in the device, including the static, standby, and dynamic power. Total thermal power includes only the thermal component for the I/O worksheet and does not include external power dissipation, such as from voltage-referenced termination resistors.

The static power (PSTATIC) is the thermal power dissipated on the chip, independent of design activity. PSTATIC includes the static power from all FPGA functional blocks, except for I/O DC bias power and transceiver DC bias power, which are included in the standby power of the I/O and XCVR worksheets, respectively. PSTATIC is the only thermal power component that varies with junction temperature and power characteristics (process). PSTATIC is also the only thermal power component that varies significantly with selected device.

Table 4.  Thermal Power (W) Information
Column Heading Description
Logic Displays the dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and associated routing. Click Logic to see details.
RAM Displays the dynamic power consumed by RAMs and associated routing. Click RAM to see details.
DSP Displays the dynamic power consumed by digital signal processing (DSP) blocks and associated routing. Click DSP to see details.
Clock Displays the dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device. Click Clock to see details.
PLL Displays the dynamic power consumed by phase-locked loops (PLLs). Click PLL to see details.
I/O Displays the thermal power consumed by I/O pins and I/O subsystems. Click I/O to see details.
XCVR Displays the total power consumed by transceiver blocks. Click XCVR to see details.
HPS Displays the total power consumed by the HPS system.
HBM Total power consumed by high-bandwidth memory (HBM) blocks and UIBs. Click the HBM button to display details.
PSTATIC Displays the static power consumed regardless of clock frequency. This includes static power consumed by I/O and transceiver blocks, but does not include standby power. PSTATIC is affected by junction temperature, selected device, and power characteristics.
Note: For information on measuring the static power consumption of a specific device, refer to the appendix Measuring Static Power.
Total Power Before SmartVID Savings The total power consumption before SmartVID power savings. Includes static power (PSTATIC) and power consumed by different blocks as reported above. Does not include power dissipated in off-chip termination resistors.
SmartVID Power Savings

Displays the total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result.

The reduction reported in this field is already taken into consideration in the Total (W) field.

The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum.

TOTAL (W) Total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors.
Note: If any thermal power value is highlighted in red, it indicates an error in the design specification. Review the relevant worksheet for errors or utilization values exceeding 100%. Correct any errors to obtain reliable power and temperature estimates.

The Thermal Analysis Summary section displays the junction temperature (TJ) and other thermal parameters, depending on the thermal analysis mode.

Table 5.  Thermal Analysis Summary
Column Heading Description
Junction Temp Mode

Select whether you provide the junction temperature, or whether detailed thermal analysis should be performed to determine junction temperature. In user-entered mode, the junction temperatures for all dies in the package are assumed to have one value, which you provide. When using a detailed thermal model, temperatures of different dies may be different, depending on the characteristics of a specific design. You can select detailed thermal mode only if the Power Characteristics field is set to Maximum, and the selected device supports a detailed thermal model.

Tip: For faster responsiveness from the system, you should leave this value as User Entered until you are ready to perform detailed thermal analysis.
User-Entered Junction Temp, TJ (°C) Specify the junction temperature for all dies in the package.
Note: This field is applicable only when the selected Junction Temp Mode value is User Entered.
Ambient Temp, TA (°C) Specifies the temperature of the air that is cooling the device.
Note: This field is applicable only when the selected Junction Temp Mode value is Detailed Thermal Model.
Max. Junction Temp TJ-MAX (°C) Specifies the maximum junction temperature that no part of any die in the package should exceed.
Note: This field is applicable only when the selected Junction Temp Mode value is Detailed Thermal Model.
Recommended ψCA(°C/W) ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature.
Note: This field is applicable only when the selected Junction Temp Mode value is Detailed Thermal Model.
Max. ψJC(°C/W) ψJC is the thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. This field shows the maximum ΨJC among all die, assuming the recommended ΨCA value above.
Note: This field is applicable only when the selected Junction Temp Mode value is Detailed Thermal Model.
Case Temperature TCASE (°C) The case temperature, which is the temperature at the top center of the integrated heat spreader, assuming the recommended ΨCA value listed above.
Note: This field is applicable only when the selected Junction Temp Mode value is Detailed Thermal Model.

Note:

You can directly enter or automatically compute junction temperatures based on the information provided. To enter the junction temperature, select User Entered in the Junction Temp Mode field, then enter the desired junction temperature in the User-Entered Junction Temp TJ (°C) field in the Thermal Analysis Summary section. In this mode, the junction temperatures for all dies in the package are assumed to have the specified value. To automatically compute junction temperatures, select Detailed Thermal Model in the same field. Refer to the Thermal worksheet for more information about detailed thermal modeling.

Table 6.  Control Button Descriptions
Button Name Description
Logic Opens the Logic worksheet to display details of the dynamic power consumed by adaptive logic modules (ALMs), flipflops, and associated routing.
RAM Opens the RAM worksheet to display details of the dynamic power consumed by RAMs and associated routing.
DSP Opens the DSP worksheet to display details of the dynamic power consumed by digital signal processing blocks and associated routing.
Clock Opens the Clock worksheet to display details of the dynamic power consumed by clock networks and associated routing.
PLL Opens the PLL worksheet to display details of the dynamic power consumed by phase-locked loops and associated routing.
I/O Opens the I/O worksheet to display details of the thermal power consumed by I/O pins and I/O subsystems.
XCVR Opens the XCVR worksheet to display details of the total power consumed by transceiver blocks.
HPS Opens the HPS worksheet to display details of the total power consumed by the HPS system.
HBM Opens the HBM worksheet to display details of the total power consumed by high-bandwidth memory blocks and UIBs.
Reset Resets the Early Power Estimator to default values; any parameters that you have specified are lost.
Import CSV Allows you to import parameters from a comma-separated value file.
Export CSV Allows you to export parameters to a comma-separated value file.
View Report Displays the Report worksheet.
Thermal Analysis Details Displays the detailed thermal analysis, on the Thermal worksheet.
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