Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

Download PDF
ID 683175
Date 12/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices 2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices 3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices 5. Factors Affecting the Accuracy of the Early Power Estimator 6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices x
1.1. Intel® Stratix® 10 EPE Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices 2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator
2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface x
3.1. Intel® Stratix® 10 EPE Input Fields 3.2. Intel® Stratix® 10 EPE Output Fields 3.3. Intel® Stratix® 10 EPE Input/Output Fields 3.4. Intel® Stratix® 10 EPE Field Shading 3.5. Intel® Stratix® 10 EPE Input Field Dependencies 3.6. Intel® Stratix® 10 EPE Buttons
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices x
4.1. Intel® Stratix® 10 EPE - Common Worksheet Elements 4.2. Intel® Stratix® 10 EPE - Main Worksheet 4.3. Intel® Stratix® 10 EPE - Logic Worksheet 4.4. Intel® Stratix® 10 EPE - RAM Worksheet 4.5. Intel® Stratix® 10 EPE - DSP Worksheet 4.6. Intel® Stratix® 10 EPE - Clock Worksheet 4.7. Intel® Stratix® 10 EPE - PLL Worksheet 4.8. Intel® Stratix® 10 EPE - I/O Worksheet 4.9. Intel® Stratix® 10 EPE - I/O-IP Worksheet 4.10. Intel® Stratix® 10 EPE - XCVR Worksheet 4.11. Intel® Stratix® 10 EPE - HPS Worksheet 4.12. Intel® Stratix® 10 EPE - HBM Worksheet 4.13. Intel® Stratix® 10 EPE - Thermal Worksheet 4.14. Intel® Stratix® 10 EPE - Report Worksheet 4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator x
5.1. Toggle Rate 5.2. Temperature
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices
5. Factors Affecting the Accuracy of the Early Power Estimator
6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
A. Measuring Static Power

4.5. Intel® Stratix® 10 EPE - DSP Worksheet

Each row in the DSP worksheet of the Early Power Estimator for Intel® Stratix® 10 devices represents a DSP design module where all instances have the same configuration, clock frequency, toggle percentage, and register usage.
Figure 11. DSP Worksheet of the Early Power Estimator


Table 9.  DSP Worksheet Information
Column Heading Description
Module

Enter a name for the DSP module in this column. This is an optional value.

Configuration Select the DSP block configuration for the module.
# of Instances

Enter the number of DSP block instances that have the same configuration, clock frequency, toggle percentage, and register usage. This value is not necessarily equal to the number of dedicated DSP blocks you use. For example, it is possible to use two 18 × 18 simple multipliers that are implemented in the same DSP block in the FPGA devices. In this case, the number of instances would be two.

To determine the maximum number of instances you can fit in the device for any particular mode, follow these steps:

  1. Open the “Variable Precision DSP Blocks” chapter of the Intel® Stratix® 10 Device Handbook.
  2. In the “Number of DSP Blocks” table, take the maximum number of DSP blocks available in the device for the mode of operation.
  3. Divide the maximum number by the “# of Mults” for that mode of operation from the “DSP Block Operation Modes” table. The resulting value is the maximum number of instances supported by the device.
Clock Freq (MHz)

Enter the clock frequency for the module (in MHz). This value is limited by the maximum frequency specification for the device family.

Toggle %

Enter the average percentage of DSP data outputs toggling on each clock cycle. The toggle percentage ranges from 0 to 50%. The default value is 12.5%. For a more conservative power estimate, use a higher toggle percentage.

50% corresponds to a randomly changing signal, since half the time the signal holds the same value and thus not transition. This is considered the highest meaningful toggle rate for a DSP block.

Preadder? Select Yes if the PreAdder function of the DSP block is turned on.
Coefficient? Select Yes if the Coefficient function of the DSP block is turned on.
Registered Stages

Select number of the registered stages. Having more stages registered increases DSP fMAX and reduces power consumption at the cost of increased latency.

  • 0—None
  • 1—Input
  • 2—Input and Output
  • 3—Input, Output, and Multiplier
  • 4— Input, Output, Multiplier, and Pipeline Stage 2
  • 5—Input, Output, Multiplier, Pipeline Stage 2, and Floating-Point Adder
Thermal Power (W)–Routing

Indicates the power dissipation due to estimated routing (in W).

Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power estimate based on observed behavior across more than 100 real-world designs.

Thermal Power (W)–Block

Indicates the estimated power consumed by the DSP blocks (in W).

Thermal Power (W)–Total

Indicates the estimated power (in W), based on information entered into the EPE spreadsheet. It is the total power consumed by the DSP blocks and is equal to the routing power and block power.

User Comments Enter any comments. This is an optional entry.

Level Two Title