Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

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ID 683175
Date 12/03/2021
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Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices 2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices 3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices 5. Factors Affecting the Accuracy of the Early Power Estimator 6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices x
1.1. Intel® Stratix® 10 EPE Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices 2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator
2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface x
3.1. Intel® Stratix® 10 EPE Input Fields 3.2. Intel® Stratix® 10 EPE Output Fields 3.3. Intel® Stratix® 10 EPE Input/Output Fields 3.4. Intel® Stratix® 10 EPE Field Shading 3.5. Intel® Stratix® 10 EPE Input Field Dependencies 3.6. Intel® Stratix® 10 EPE Buttons
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices x
4.1. Intel® Stratix® 10 EPE - Common Worksheet Elements 4.2. Intel® Stratix® 10 EPE - Main Worksheet 4.3. Intel® Stratix® 10 EPE - Logic Worksheet 4.4. Intel® Stratix® 10 EPE - RAM Worksheet 4.5. Intel® Stratix® 10 EPE - DSP Worksheet 4.6. Intel® Stratix® 10 EPE - Clock Worksheet 4.7. Intel® Stratix® 10 EPE - PLL Worksheet 4.8. Intel® Stratix® 10 EPE - I/O Worksheet 4.9. Intel® Stratix® 10 EPE - I/O-IP Worksheet 4.10. Intel® Stratix® 10 EPE - XCVR Worksheet 4.11. Intel® Stratix® 10 EPE - HPS Worksheet 4.12. Intel® Stratix® 10 EPE - HBM Worksheet 4.13. Intel® Stratix® 10 EPE - Thermal Worksheet 4.14. Intel® Stratix® 10 EPE - Report Worksheet 4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator x
5.1. Toggle Rate 5.2. Temperature
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices
5. Factors Affecting the Accuracy of the Early Power Estimator
6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
A. Measuring Static Power

4.4. Intel® Stratix® 10 EPE - RAM Worksheet

Each row in the RAM worksheet of the Early Power Estimator (EPE) for Intel® Stratix® 10 devices represents a design module with RAM blocks of the same type, same data width, same RAM depth (if applicable), same RAM mode, and the same port parameters.

Each row in the RAM worksheet of the EPE spreadsheet represents a logical RAM module that you can implement using one or more physical RAM blocks. The EPE spreadsheet implements each logical RAM module with the minimum number of physical RAM blocks, in the most power-efficient way possible, based on the specified logical width and depth.

You must know how your RAM is implemented by the Intel® Quartus® Prime Compiler when you are selecting the RAM block mode. For example, if a ROM is implemented with two ports, it is considered a true dual-port memory and not a ROM. Single-port and ROM implementations use only one port. Simple dual-port and true dual-port implementations use both Port A and Port B.

Note:

  • The Early Power Estimator reports MLAB power in the RAM worksheet. However the Intel® Quartus® Prime Power Analyzer reports MLAB power as Combinational cell and Register cell block type in the Thermal Power Dissipation by Block Type section of the power report.
  • The Intel® Quartus® Prime Power Analyzer reports LAB clock power as Block Thermal Dynamic Power under Clock Network block type in the Thermal Power Dissipation by Block Type section of the power report. The Early Power Estimator reports LAB clock power in either the Clock or RAM worksheet, depending on whether the LAB is used to implement logic or used as MLAB, respectively.
Figure 10. RAM Worksheet of the Early Power Estimator


Table 8.  RAM Worksheet Information
Column Heading Description
Module

Enter a name for the RAM module in this row. This is an optional value.

RAM Type

Select the implemented RAM type.

You can find the RAM type in the Type column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Place Stage > Fitter RAM Summary.

# RAM Blocks

Enter the number of RAM blocks in the module that use the same type and mode and have the same parameter for each port. The parameters for each port are as follows:

  • Clock frequency in MHz
  • Percentage of time the RAM is enabled
  • Percentage of time the port is writing as opposed to reading

You can find the number of RAM blocks in either the MLAB cells or M20K blocks column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Place Stage > Fitter RAM Summary.

Note: The value entered into this field represents the number of logical memory blocks. Depending on the specified memory depth and data width, more than one physical memory block may be required to implement one logical block. The Early Power Estimator calculates the number of physical memory blocks based on the specified memory depth and data width, such that the minimum number of physical blocks is used, and assuming the most power efficient physical configuration.
Data Width

Enter the width of the data for the RAM block. This value is limited based on the RAM type. You can find the width of the RAM block in the Port A Width or the Port B Width column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Place Stage > Fitter RAM Summary.

For RAM blocks that have different widths for Port A and Port B, use the larger of the two widths.

RAM Depth

Enter the depth of the RAM block in number of words.

You can find the depth of the RAM block in the Port A Depth or the Port B Depth column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Place Stage > Fitter RAM Summary.

RAM Mode

Select from the following modes:

  • Single Port
  • Simple Dual Port
  • True Dual Port
  • Simple Dual Port with ECC
  • ROM
  • Simple Quad Port

The mode is based on how the Intel® Quartus® Prime Compiler implements the RAM. If you are unsure how your memory module is implemented, you can compile a test case in the required configuration in the Intel® Quartus® Prime software. You can find the RAM mode in the Mode column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Place Stage > Fitter RAM Summary.

A single-port RAM has one port with a read and a write control signal. A simple dual-port RAM has one read port and one write port. A true dual-port RAM has two ports, each with a read and a write control signal. ROMs are read-only single-port RAMs. A simple quad-port RAM has a total of four ports, two read ports and two write ports.

Port A - Clock Freq (MHz)

Enter the clock frequency for Port A of the RAM blocks (in MHz). This value is limited by the maximum frequency specification for the RAM type and device family.

Port A - Enable %

The average percentage of time the Port A clock enable is active, regardless of activity on RAM data and address inputs. This number must be a percentage between 0% and 100%. RAM power is consumed primarily when a clock event occurs. Using a clock enable signal to disable a port when no read or write operation is occurring can result in significant power savings.

Port A - Read %

Enter the percentage of time Port A of the RAM block is in read mode. This field is applicable only for single port and true dual port RAMs.

This value must be a percentage number between 0 and 100%.

Port A - Write %

Enter the average percentage of time Port A of the RAM block is in write mode. This field applies only for single port, dual port and true dual port RAMs.

This value must be a percentage number between 0 and 100%.

Port B - Clock Freq (MHz)

Enter the clock frequency for Port B of the RAM blocks (in MHz).

Port B - Enable %

Enter the average percentage of time the input clock enable for Port B is active, regardless of the activity on the RAM data and address inputs. The enable percentage ranges from 0 to 100%.

RAM power is consumed primarily when a clock event occurs. Using a clock-enable signal to disable a port when no read or write operation is occurring can result in significant power savings.

Port B - Read %

Enter the percentage of time Port B of the RAM block is in read mode. This field is applicable only to dual port and true dual port RAMs and ROMs.

This value must be a percentage number between 0 and 100%.

Port B - Write %

Enter the percentage of time Port B of the RAM block is in write mode. This field is available only for true dual-port mode.

This value must be a percentage number between 0 and 100%.

Port C - Write %

Enter the percentage of time the RAM block is writing to this port. In Simple Quad-Port Mode, clock and clock enable for all parts are shared and the same as Port A.

This value must be a percentage number between 0 and 100%.

Port D - Read %

Enter the percentage of time the RAM block is reading on this port. In Simple Quad-Port Mode, clock and clock enable for all parts are shared and the same as Port A.

This value must be a percentage number between 0 and 100%.

Toggle %

The percentage of clock cycles when the block output signal changes value. This value is multiplied by the clock frequency and the enable percentage to determine the number of transitions per second. This value affects only routing power.

50% corresponds to a randomly changing signal, since half the time the signal holds the same value and thus not transition. This is considered the highest meaningful toggle rate for a RAM block.

Thermal Power (W) - Routing

Indicates the power dissipation due to estimated routing (in W).

Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power estimate based on observed behavior across more than 100 real-world designs.

Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact routing used in your design.

Thermal Power (W) - Block

Indicates the power dissipation due to internal toggling of the RAM (in W).

Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact RAM modes in your design.

Thermal Power (W) - Total

Indicates the estimated power (in W), based on information entered into the EPE spreadsheet. Total power is equal to the sum of routing power and block power.

User Comments

Enter any comments. This is an optional entry.

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