25G Ethernet Stratix® 10 Intel® FPGA IP User Guide

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ID 683154
Date 6/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide

7.1. PHY Registers

Table 25.  PHY RegistersThe global hard reset csr_rst_n resets all of these registers. The TX reset tx_rst_n and RX reset rx_rst_n signals do not reset these registers.
Addr Name Description Reset Access
0x300 REVID IP core PHY module revision ID

0x0504 2018

 RO
0x301 SCRATCH Scratch register available for testing 0x0000 0000 RW
0x302 PHY_NAME_0 First characters of IP core variation identifier string, "0025". The "00" is unprintable. 0x0000 3235 RO
0x303 PHY_NAME_1 Next characters of IP core variation identifier string, "00GE". The "00" is unprintable. 0x0000 4745 RO
0x304 PHY_NAME_2 Final characters of IP core variation identifier string, "0pcs". The "0" is unprintable. 0x0070 6373 RO
0x310 PHY_CONFIG PHY configuration registers. The following bit fields are defined:
  • Bit[0]: eio_sys_rst. Full system reset (except registers). Set this bit to initiate the internal reset sequence.
  • Bit[1]: soft_txp_rst. TX soft reset. Resets TX PCS, MAC, and adapter.
  • Bit[2]: soft_rxp_rst. RX soft reset. Resets RX PCS, MAC, and adapter.
  • Bit[3]: Reserved.
  • Bit[4]: set_ref_lock. Directs the RX CDR PLL to lock to the reference clock.
  • Bit[5]: set_data_lock. Directs the RX CDR PLL to lock to data.
  • Bits[31:6]: Reserved.
 26'hX_2'b0_1'bX_3'b0 3 RW
0x312 WORD_LOCK When asserted, indicates that the virtual channel has identified 66 bit block boundaries in the serial data stream. 31'hX1'b0 3 RO
0x313 EIO_SLOOP Serial PMA loopback. Setting a bit puts the corresponding transceiver in serial loopback mode. In serial loopback mode, the TX lane loops back to the RX lane on an internal loopback path. 31'hX1'b0 3 RW
0x314 EIO_FLAG_SEL Supports indirect addressing of individual FIFO flags in the PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the EIO_FLAGS register.

The value in the EIO_FLAG_SEL register directs the IP core to make available the following FIFO flag:

  • 3'b000: TX FIFO full
  • 3'b001: TX FIFO empty
  • 3b010: TX FIFO partially full
  • 3'b011: TX FIFO partially empty
  • 3b100: RX FIFO full
  • 3b101: RX FIFO empty
  • 3b110: RX FIFO partially full
  • 3b111: RX FIFO partially empty
 29'hX3'b0 3 RW
0x315 EIO_FLAGS PCS indirect data. To read a FIFO flag, set the value in the EIO_FLAG_SEL register to indicate the flag you want to read. After you specify the flag in the EIO_FLAG_SEL register, each bit [n] in the EIO_FLAGS register has the value of that FIFO flag for the transceiver channel for lane [n]. 31'hX1'b0 3 RO
0x321 EIO_FREQ_LOCK Each asserted bit indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked. 31'hX1'b0 3 RO
0x322 PHY_CLK The following encodings are defined:
  • Bit[0]: Indicates if the TX PCS is ready.
  • Bit[1]: Indicates if the TX MAC PLL is locked.
  • Bit[2]: Indicates if the RX CDR PLL is locked.
29'hX3'b00 3 RO
0x323 FRM_ERR The IP core asserts bit [0] if it identifies a frame error. You can read this register to determine if the IP core sustains a low number of frame errors, below the threshold to lose word lock. This bit is sticky, unless the IP core loses word lock. Write 1'b1 to the SCLR_FRM_ERR register to clear.

If the IP core loses word lock, it clears this register.

 31'hX1'b0 3 RO
0x324 SCLR_FRM_ERR Synchronous clear for FRM_ERR register. Write 1'b1 to this register to clear the FRM_ERR register and bit [1] of the LANE_DESKEWED register. A single bit clears all sticky framing errors.

This bit does not auto-clear. Write a 1'b0 to continue logging frame errors.

0x0

 RW
0x325 EIO_RX_SOFT_PURGE_S

Reserved.

 0x0000 RO
0x326 RX_PCS_FULLY_ALIGNED_S Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit[0]: RX PCS fully aligned status.
  • Bit[1]: RX PCS bit error rate status. A bit value of 1 indicates a bit error rate higher than 10-4 or there are at least 16 errors within 50 us. This bit value is only valid when the link fault generation is enabled.

31'hX1'b0 3

RO
0x329 LANE_DESKEWED
The following encodings are defined:
  • Bit[0]: Indicates all lanes are deskewed.
  • Bit[1]: When asserted indicates a change in lanes deskewed status. To clear this sticky bit, write 1'b1 to the corresponding bit of the SCLR_FRM_ERR register. This is a latched signal.

30'hX2'b00 3

RO
0x340 Reserved
0x341 KHZ_RX The register indicates the value of RX clock (clk_rxmac) frequency. Apply the following definition for the frequency value:

[(Register value 4 * clk_status)/10] KHZ

0x0000 0000 RO
0x342 KHZ_TX The register indicates the value of TX clock (clk_txmac) frequency. Apply the following definition for the frequency value:

[(Register value 4 * clk_status)/10] KHZ

0x0000 0000 RO
0x343 PHY_TLKIT_ACCESS If you turn on the Enable auto adaptation triggering for RX PMA CTLE/DFE mode option, write 1'b1 to bit[0] of this register to hold the auto adaptation module FSM to an idle state.
Note: For H-tile production devices, write 1'b1 to bit[0] before you launch the Transceiver Toolkit so that the transceiver channel appears in the Transceiver Toolkit. Close the Transceiver Toolkit before you write 1'b0 to bit[0] to restart the auto adaptation module FSM so that the System Console does not hang. For more information, refer to Disabling Background Calibration and Accessing the Native PHY in L- and H-Tile Devices.
31'hX 1'b0 RW
3 X means "Don't Care".
4 Register value convert in decimal.
Level Two Title