Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/18/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.9.1. PMA Features

PMA channels are comprised of transmitter (TX), receiver (RX), and high speed clocking resources.

Intel® Stratix® 10 MX transmitter (TX) features provide exceptional signal integrity at data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ. Clocking options include ultra-low jitter LC tank-based (ATX) PLLs with optional fractional synthesis capability, channel PLLs operating as clock multiplier units (CMUs), and fractional synthesis PLLs (fPLLs).

  • ATX PLL—can be configured in integer mode, or optionally, in a new fractional synthesis mode. Each ATX PLL spans the full frequency range of the supported data rate range providing a stable, flexible clock source with the lowest jitter.
  • CMU PLL—when not being used as a transceiver, select PMA channels can be configured as channel PLLs operating as CMUs to provide an additional master clock source within the transceiver bank.
  • fPLL—In addition, dedicated fPLLs are available with precision frequency synthesis capabilities. fPLLs can be used to synthesize multiple clock frequencies from a single reference clock source and replace multiple reference oscillators for multi-protocol and multi-rate applications.

On the receiver side, each PMA has an independent channel PLL that allows analog tracking for clock-data recovery. Each PMA also has advanced equalization circuits that compensate for transmission losses across a wide frequency spectrum.

  • Variable Gain Amplifier (VGA)—to optimize the receiver's dynamic range
  • Continuous Time Linear Equalizer (CTLE)—to compensate for channel losses with lowest power dissipation
  • Decision Feedback Equalizer (DFE)—to provide additional equalization capability on backplanes even in the presence of crosstalk and reflections
  • On-Die Instrumentation (ODI)—to provide on-chip eye monitoring capabilities (Eye Viewer). This capability helps to optimize link equalization parameters during board bring-up and supports in-system link diagnostics and equalization margin testing
Figure 12.  Intel® Stratix® 10 MX Receiver Block Features


All link equalization parameters feature automatic adaptation using the new Advanced Digital Adaptive Parametric Tuning (ADAPT) circuit. This circuit is used to dynamically set DFE tap weights, adjust CTLE parameters, and optimize VGA gain and threshold voltage. Finally, optimal and consistent signal integrity is ensured by using the new hardened Precision Signal Integrity Calibration Engine (PreSICE) to automatically calibrate all transceiver circuit blocks on power-up. This gives the most link margin and ensures robust, reliable, and error-free operation.

Table 6.  Transceiver PMA Features

Feature

Capability

Chip-to-Chip Data Rates

1 Gbps 7 to 57.8 Gbps PAM4 / 28.9 Gbps NRZ

Backplane Support

Drive backplanes at data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ, including 10GBASE-KR compliance

Optical Module Support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, QSFPDD, CFP/CFP2/CFP4

Cable Driving Support

SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis

5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear Equalizer (CTLE)

Dual mode, high-gain, and high-data rate, linear receive equalization to compensate for system channel loss

Decision Feedback Equalizer (DFE)

15 fixed tap DFE to equalize backplane channel loss in the presence of crosstalk and noisy environments

Advanced Digital Adaptive Parametric Tuning (ADAPT)

Fully digital adaptation engine to automatically adjust all link equalization parameters—including CTLE, DFE, and VGA blocks—that provide optimal link margin without intervention from user logic

Precision Signal Integrity Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on power-up, which provides the optimal signal integrity and jitter performance

ATX Transmit PLLs

Low jitter ATX (inductor-capacitor) transmit PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols, with optional fractional frequency synthesis capability

Fractional PLLs

On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost

Digitally Assisted Analog CDR

Superior jitter tolerance with fast lock time

On-Die Instrumentation— Eye Viewer and Jitter Margin Tool

Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution eye monitoring (Eye Viewer). Also inject jitter from transmitter to test link margin in system.

Dynamic Reconfiguration

Allows for independent control of each transceiver channel Avalon memory-mapped interface for the most transceiver flexibility.

Multiple PCS-PMA and PCS-Core to FPGA fabric interface widths

8, 10, 16, 20, 32, 40, or 64 bit interface widths for flexibility of deserialization width, encoding, and reduced latency

7 Stratix 10 transceivers can support data rates below 1 Gbps with over sampling.
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