Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

Download PDF
ID 683149
Date 8/18/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.1. Intel® Stratix® 10 MX Devices

In addition to delivering up to 512 Gigabyte/s of 3D stacked HBM2 DRAM memory bandwidth in a single package, Intel® Stratix® 10 MX devices offer up to 1 GHz core fabric performance and contain up to 2.1 million LEs in a monolithic fabric. They also feature up to 96 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The dual mode transceivers are capable of data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for both short reach and backplane driving applications.

These devices are optimized for FPGA applications that require the highest memory and transceiver bandwidth, and the highest core fabric performance, with the power efficiency of Intel 14 nm tri-gate process technology.

The high-performance monolithic FPGA fabric is based on the new Intel® Hyperflex™ core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel's adaptive logic module (ALM) and a rich set of high performance building blocks including:

  • eSRAM (47.25 Mbit) embedded memory blocks
  • M20K (20 Kb) embedded memory blocks
  • Variable precision DSP blocks with IEEE 754 compliant hard floating-point
  • Fractional synthesis and integer PLLs
  • Hard memory controllers and PHY for external memory interfaces
  • General purpose IO cells

To clock these building blocks, Intel® Stratix® 10 MX devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating. The high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Intel® Stratix® 10 MX devices contain hard PCI Express* IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC hard IP, which free up valuable core logic resources, save power, and increase your productivity.

Level Two Title