1.9.2. PCS Features
Intel® Stratix® 10 MX PMA channels interface with core logic through configurable and bypassable PCS interface layers.
The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. This feature provides the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64 bit interface width between each transceiver and the core logic.
The PCS also contains hard IP to support a variety of standard and proprietary protocols across a wide range of data rates and encoding schemes. The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4 Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding and support for data rates up to 28.9 Gbps.
For more information about the PCS-Core interface or the double rate transfer mode, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide, and the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide.
PCS Protocol Support |
Data Rate (Gbps) |
Transmitter Data Path |
Receiver Data Path |
---|---|---|---|
Standard PCS |
1 to 12.5 |
Phase compensation FIFO, byte serializer, 8B/10B encoder, bit-slipper, channel bonding |
Rate match FIFO, word-aligner, 8B/10B decoder, byte deserializer, byte ordering |
PCI Express Gen1/Gen2 x1, x2, x4, x8, x16 |
2.5 and 5.0 |
Same as Standard PCS plus PIPE 2.0 interface to core |
Same as Standard PCS plus PIPE 2.0 interface to core |
PCI Express Gen3 x1, x2, x4, x8, x16 |
8.0 |
Phase compensation FIFO, byte serializer, encoder, scrambler, bit-slipper, gear box, channel bonding, and PIPE 3.0 interface to core, auto speed negotiation |
Rate match FIFO (0-600 ppm mode), word-aligner, decoder, descrambler, phase compensation FIFO, block sync, byte deserializer, byte ordering, PIPE 3.0 interface to core, auto speed negotiation |
CPRI |
0.6144 to 9.8 |
Same as Standard PCS plus deterministic latency serialization |
Same as Standard PCS plus deterministic latency deserialization |
Enhanced PCS |
2.5 to 17.4 |
FIFO, channel bonding, bit-slipper, and gear box |
FIFO, block sync, bit-slipper, and gear box |
10GBASE-R |
10.3125 |
FIFO, 64B/66B encoder, scrambler, FEC, and gear box |
FIFO, 64B/66B decoder, descrambler, block sync, FEC, and gear box |
Interlaken |
4.9 to 17.4 |
FIFO, channel bonding, frame generator, CRC-32 generator, scrambler, disparity generator, bit-slipper, and gear box |
FIFO, CRC-32 checker, frame sync, descrambler, disparity checker, block sync, and gear box |
SFI-S/SFI-5.2 |
11.3 |
FIFO, channel bonding, bit-slipper, and gear box |
FIFO, bit-slipper, and gear box |
IEEE 1588 |
1.25 to 10.3125 |
FIFO (fixed latency), 64B/66B encoder, scrambler, and gear box |
FIFO (fixed latency), 64B/66B decoder, descrambler, block sync, and gear box |
SDI |
up to 12.5 |
FIFO and gear box |
FIFO, bit-slipper, and gear box |
GigE |
1.25 |
Same as Standard PCS plus GigE state machine |
Same as Standard PCS plus GigE state machine |
PCS Direct | up to 28.9 | Custom | Custom |