Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/18/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.15. Adaptive Logic Module (ALM)

Intel® Stratix® 10 MX devices use a similar adaptive logic module (ALM) as the previous generation Intel® Arria® 10 and Stratix® V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

Figure 14. ALM Block Diagram


Key features and capabilities of the ALM include:

  • High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Intel® Hyperflex™ architecture, enables Intel® Stratix® 10 MX devices to maximize core performance at very high core logic utilization
  • Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization

The Intel® Quartus® Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel® Quartus® Prime software simplifies design reuse as it automatically maps legacy designs into the Intel® Stratix® 10 MX ALM architecture.

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