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1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
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1.5.1. DDR Device Configuration
The following sections describe how the DDR registers are configured in the Stratix series and APEX II devices.