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1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
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1.2.1. DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory
DDR SDRAM, DDR2 SDRAM, and RLDRAM II write and read data at twice the clock rate by capturing data on both the positive and negative edge of a clock.
DDR and DDR2 SDRAM are JEDEC standards. RLDRAM II devices have minimal latency to support designs that require fast response times. These DDR memory interfaces use a variety of I/O standards, such as SSTL-II, 1.8-V HSTL, LVTTL, and LVCMOS.
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