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1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
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1.8. ALTDDIO_OUT IP Core Signals
This figure shows the ports for the ALTDDIO_OUT IP core.
Figure 10. ALTDDIO_OUT Signals
These tables list the input and output ports for the ALTDDIO_OUT IP core.
Name | Required | Description |
---|---|---|
datain_h[] | Yes | Input data for rising edge of outclock port. Input port WIDTH wide. |
datain_l[] | Yes | Input data for falling edge of outclock port. Input port WIDTH wide. |
outclock | Yes | Clock signal to register data output. dataout port outputs DDR data on each level of outclock signal. |
outclocken | No | Clock enable for outclock port. |
aclr | No | Asynchronous clear input. The aclr and aset ports cannot be connected at the same time. |
aset | No | Asynchronous set input. The aclr and aset ports cannot be connected at the same time. |
oe | No | Output enable for the dataout port. Active-high signal. You can add an inverter if you need an active-low oe. |
sclr | No | Synchronous clear input. The sclr and sset ports cannot be connected at the same time. The sclr port is available for Arria® GX, Stratix® III, Stratix® II, Stratix® II GX, Stratix® , Stratix® GX, HardCopy II, and HardCopy Stratix® devices only. |
sset | No | Synchronous set input. The sclr and sset ports cannot be connected at the same time. The sset port is available for Arria® GX, Stratix® III, Stratix® II, Stratix® II GX, Stratix® , Stratix® GX, HardCopy II, and HardCopy Stratix® devices only. |
Name | Required | Description |
---|---|---|
dataout[] | Yes | DDR output data port. Output port WIDTH wide. dataout port should directly feed an output pin in top-level design. |
oe_out | No | Output enable for the bidirectional padio port. Output port [WIDTH–1..0] wide. This port is available for Stratix® III and Cyclone® III devices only. |