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1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
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1.5.1.2. Output Configuration
The dedicated output registers for Stratix® series and APEX™ II devices are labeled AO and BO. These positive-edge triggered registers and a multiplexer are used to implement the output path for DDR I/O.
Figure 3. Output DDR I/O Path Configuration for Stratix Series and APEX II DevicesThis figure shows the IOE configuration for DDR outputs in Stratix® series and APEX™ II devices.
On the positive edge of the clock, a high data bit and a low data bit are captured in registers AO and BO. The outputs of these two registers are fed to the input of a 2-to-1 multiplexer, which uses the output register clock as its control signal. A high clock selects the data in register BO, and a low level of the clock selects the data in register AO. This process doubles the data at the I/O pin.
Figure 4. Stratix IOE in DDR Output I/O ConfigurationThis figure shows the IOE configuration for DDR outputs in Stratix® series devices