Visible to Intel only — GUID: eis1415169153557
Ixiasoft
1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
Visible to Intel only — GUID: eis1415169153557
Ixiasoft
1.1. ALTDDIO Features
The ALTDDIO IP cores implement a DDR interface and offer the following additional features:
- The ALTDDIO_IN IP core receives data on both edges of the reference clock
- The ALTDDIO_OUT IP core transmits data on both edges of the reference clock
- The ALTDDIO_BIDIR IP core transmits and receives data on both edges of the reference clock
- Asynchronous clear and asynchronous set input options available
- Synchronous clear and synchronous set input options available for Arrix GX and Stratix series devices.
- inclock signal to sample the DDR input
- outclock signal to register the data output
- Clock enable signals
- Bidirectional port for the ALTDDIO_BIDIR IP core
- An output enable input for the ALTDDIO_OUT and ALTDDIO_BIDIR IP cores