Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.1. ALTDDIO Features

The ALTDDIO IP cores implement a DDR interface and offer the following additional features:

  • The ALTDDIO_IN IP core receives data on both edges of the reference clock
  • The ALTDDIO_OUT IP core transmits data on both edges of the reference clock
  • The ALTDDIO_BIDIR IP core transmits and receives data on both edges of the reference clock
  • Asynchronous clear and asynchronous set input options available
  • Synchronous clear and synchronous set input options available for Arrix GX and Stratix series devices.
  • inclock signal to sample the DDR input
  • outclock signal to register the data output
  • Clock enable signals
  • Bidirectional port for the ALTDDIO_BIDIR IP core
  • An output enable input for the ALTDDIO_OUT and ALTDDIO_BIDIR IP cores