Quartus® Prime Pro Edition User Guide: Design Constraints
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Ixiasoft
Visible to Intel only — GUID: jbv1602191452229
Ixiasoft
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis
After instantiating the component IP in a top-level project design file (for example, top.v), you run the Design Analysis compilation stage to elaborate the design RTL to extract component IP and target device information. Upon launch, Tile Interface Planner initializes and displays this component IP information in the Design Tree view.
- Open or create an Quartus® Prime project that includes component IP targeting F-tile:
- Create a new project, add design files, and specify the target Agilex® 7 FPGA by clicking File > New Project Wizard.
Or
- Parameterize and instantiate component IP with IP Catalog (View > IP Catalog) or Platform Designer (Tools > Platform Designer ).
- Create a new project, add design files, and specify the target Agilex® 7 FPGA by clicking File > New Project Wizard.
- To run the Design Analysis stage of the Compiler, double-click Design Analysis on the Compilation Dashboard (Processing > Compilation Dashboard).
Figure 37. Design Analysis Stage in Compilation Dashboard
- Initialize Tile Interface Planner, as Step 2: Initialize Tile Interface Planner describes.