Quartus® Prime Pro Edition User Guide: Design Constraints

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ID 683143
Date 11/07/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Quartus® Prime GUI 1.1.4. Specifying Timing Constraints
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify NoC Constraints in NoC Assignment Editor 1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor 1.1.2.4. Specify I/O Constraints in Pin Planner 1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.6. Adjust Constraints with the Chip Planner 1.1.2.7. Constraining Designs with the Design Partition Planner
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
1.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
1.1.2.2.1. NoC Assignment Editor Interface Controls 1.1.2.2.2. Troubleshooting NoC Assignment Editor
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner General Tool Flow 2.1.3. Interface Planner NoC Tool Flow 2.1.4. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner General Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.3. Interface Planner NoC Tool Flow x
2.1.3.1. Viewing the NoC in Interface Planner 2.1.3.2. Reporting NoC Performance
2.1.4. Interface Planner Reports x
2.1.4.1. Report Summary 2.1.4.2. Report Pins 2.1.4.3. Report HSSI Channels 2.1.4.4. Report Clocks 2.1.4.5. Report Periphery Locations 2.1.4.6. Report Cell Connectivity 2.1.4.7. Report Instance Assignments
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Constraining Dynamic Reconfiguration IP 2.2.4. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks
2.2.3. Constraining Dynamic Reconfiguration IP x
2.2.3.1. Defining a Dynamic Reconfiguration Group 2.2.3.2. Assigning Dynamic Reconfiguration Group Placement
2.2.4. Tile Interface Planner GUI Reference x
2.2.4.1. Flow Controls 2.2.4.2. Home Tab 2.2.4.3. Assignments Tab Controls 2.2.4.4. Plan Tab Controls 2.2.4.5. Tcl Console Window
2.2.4.4. Plan Tab Controls x
2.2.4.4.1. Design Tree and Filters 2.2.4.4.2. Reconfiguration Groups View 2.2.4.4.3. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel FPGA Device and I/O Terminology
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
3.2.6. Assigning Differential Pins x
3.2.6.1. Overriding I/O Placement Rules on Differential Pins
3.2.8. Entering Pin Assignments in HDL Code x
3.2.8.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
Answers to Top FAQs
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Quartus® Prime Pro Edition User Guides

1.4. Constraining Designs Revision History

Table 6.  Constraining Designs Revision History
Document Version Quartus® Prime Version Changes
2024.07.08 24.2
  • Updated Node, Entity, and Instance-Level Constraints topic for DS Assignment Editor.
  • Added new Specify Dual Simplex Assignments in DS Assignment Editor topic.
2024.04.01 24.1
  • Applied initial Altera rebranding throughout.
2023.12.04 23.4
  • Applied initial Altera rebranding throughout.
  • Added new Troubleshooting NoC Assignment Editor topic.
  • Revised the Specifying Timing Constraints topic to add introductory information and context about typical constraints.
  • Updated Pin Planner screenshot in Specify I/O Constraints in Pin Planner topic for removal of VREF Groups and Edges highlight.
2023.10.02 23.3
  • Updated What's New In This Version for enhancements to Pin Planner reporting.
  • Updated screenshots in Probing Between Components of the Quartus® Prime GUI for latest Compilation Dashboard.
  • Revised Specify NoC Constraints in NoC Assignment Editor topic for new connection flows.
2023.04.03 23.1
  • Updated What's New In This Version for NoC support and Intel Agilex 7 device family name changes.
  • Updated Node, Entity, and Instance-Level Constraints topic for NoC Assignment Editor.
  • Updated Plan Tab Controls topic for NoC View.
  • Updated Reports Tab Controls topic for NoC Performance report.
  • Added new Specify NoC Constraints in the NoC Assignment Editor topic.
  • Added new NoC Assignment Editor Interface Controls topic.
  • Updated product family name to "Intel Agilex 7."
2022.06.21 22.2
  • Added Top FAQs navigation to document cover.
  • Added What's New In This Version section to Constraining Designs topic.
2021.10.04 21.3
  • Removed obsolete Tcl-only Timing Analysis topic.
  • Updated Node, Entity, and Instance-Level Constraints topic for latest tools and Constraint Tools per Design Phase table.
  • Revised Plan Interface Constraints topic for Tile Interface Planner.
  • Revised Probing Between Components of the Quartus® Prime GUI for latest tools.
2019.10.16 19.3
  • Added "Specifying Multi-Dimensional Bus Constraints" topic.
  • Updated examples in "Create a Project and Apply Constraints."
2019.08.21 18.1 Corrected minor typo in "Tcl-only Script Flows" topic.
2019.01.04 18.1
  • Clarified default location of .sdc and .qsf files in "Constraining Designs" topic.
  • Added "Plan Interface Constraints with Interface Planner" topic.
  • Added screenshots to "Constrain Designs with the Pin Planner" and "Constrain Designs with the Chip Planner."
  • Added two new "Assigning a Pin" and "Creating a Project and Applying Constraints" topics showing Tcl examples.
  • Added link to Using Timing Constraints topic in Timing Analyzer UG that explains all of the commands
2017.11.06 17.1
  • Renamed topic: Constraining Designs with the GUI to Constraining Designs with Quartus Prime Tools.
  • Renamed topic: Global Constraints to Global Constraints and Assignments.
  • Added table: Quartus Prime Tools to Set Global Constraints.
  • Removed topic: Common Types of Global Constraints.
  • Removed topic: Settings That Direct Compilation and Analysis Flows.
  • Updated topic: Node, Entity and Instance-Level Constraints.
  • Added table: Quartus Prime Tools to Set Node, Entity and Instance Level Constraints.
  • Added topic: Assignment Editor.
  • Updated topic: Constraining Designs with the Pin Planner.
  • Updated topic: Constraining Designs with the Chip Planner.
  • Added topic: Constraining designs with the Design Partition Planner.
  • Updated topic: Probing Between Components of the Quartus Prime GUI.
  • Added example: Locate a Resource Selected in the Project Navigator.
  • Updated topic: SDC and the Timing Analyzer, and renamed to Specifying Individual Timing Constraints.
  • Added figure: Constraint Menu in Timing Analyzer.
  • Added example: Create Clock Dialog Box.
  • Updated topic: Constraining Designs with Tcl, and renamed to Constraining Designs with Tcl Scripts
  • Updated topic: Quartus Prime Settings Files and Tcl , and renamed to Generating Quartus Prime Settings Files.
  • Added example: blinking_led.qsf File.
  • Updated topic: Timing Analysis with Synopsys Design Constraints and Tcl, and renamed to Timing Analysis with .sdc Files and Tcl Scripts.
  • Added example: .sdc File with Timing Constraints.
  • Added topic: Tcl-only Script Flows.
  • Updated topic: A Fully Iterative Scripted Flow.
2017.05.08 17.0
  • Removed references to deprecated Fitter Effort logic option.
2016.10.31 16.1
  • Implemented Intel rebranding.
2015.11.02 15.1
  • Changed instances of Quartus II to Intel Quartus Prime.
June 2014 14.0 Formatting updates.
November 2012 12.1 Update Pin Planner description for task and report windows.
June 2012 12.0 Removed survey link.
November 2011 10.0 Template update.
December 2010 10.0 Template update.
July 2010 10.0 Rewrote chapter to more broadly cover all design constraint methods. Removed procedural steps and user interface details, and replaced with links to Quartus II Help.
November 2009 9.1
  • Added two notes.
  • Minor text edits.
March 2009 9.0
  • Revised and reorganized the entire chapter.
  • Added section “Probing to Source Design Files and Other Quartus Windows” on page1–2.
  • Added description of node type icons (Table1–3).
  • Added explanation of wildcard characters.
November 2008 8.1 Changed to 8½” × 11” page size. No change to content.
May 2008 8.0 Updated Quartus II software 8.0 revision and date.
Level Two Title