Quartus® Prime Pro Edition User Guide: Design Constraints

Download PDF
ID 683143
Date 11/07/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Quartus® Prime GUI 1.1.4. Specifying Timing Constraints
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify NoC Constraints in NoC Assignment Editor 1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor 1.1.2.4. Specify I/O Constraints in Pin Planner 1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.6. Adjust Constraints with the Chip Planner 1.1.2.7. Constraining Designs with the Design Partition Planner
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
1.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
1.1.2.2.1. NoC Assignment Editor Interface Controls 1.1.2.2.2. Troubleshooting NoC Assignment Editor
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner General Tool Flow 2.1.3. Interface Planner NoC Tool Flow 2.1.4. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner General Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.3. Interface Planner NoC Tool Flow x
2.1.3.1. Viewing the NoC in Interface Planner 2.1.3.2. Reporting NoC Performance
2.1.4. Interface Planner Reports x
2.1.4.1. Report Summary 2.1.4.2. Report Pins 2.1.4.3. Report HSSI Channels 2.1.4.4. Report Clocks 2.1.4.5. Report Periphery Locations 2.1.4.6. Report Cell Connectivity 2.1.4.7. Report Instance Assignments
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Constraining Dynamic Reconfiguration IP 2.2.4. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks
2.2.3. Constraining Dynamic Reconfiguration IP x
2.2.3.1. Defining a Dynamic Reconfiguration Group 2.2.3.2. Assigning Dynamic Reconfiguration Group Placement
2.2.4. Tile Interface Planner GUI Reference x
2.2.4.1. Flow Controls 2.2.4.2. Home Tab 2.2.4.3. Assignments Tab Controls 2.2.4.4. Plan Tab Controls 2.2.4.5. Tcl Console Window
2.2.4.4. Plan Tab Controls x
2.2.4.4.1. Design Tree and Filters 2.2.4.4.2. Reconfiguration Groups View 2.2.4.4.3. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel FPGA Device and I/O Terminology
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
3.2.6. Assigning Differential Pins x
3.2.6.1. Overriding I/O Placement Rules on Differential Pins
3.2.8. Entering Pin Assignments in HDL Code x
3.2.8.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
Answers to Top FAQs
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Quartus® Prime Pro Edition User Guides

1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor

For designs with supported HSSI IP targeting Agilex™ 5 FPGAs only, the Dual Simplex (DS) Assignment Editor in the Quartus® Prime Pro Edition software allows you to create and view dual simplex logical assignments according to your channel arrangement. After defining dual simplex groups in the DS Assignment Editor, you run the HSSI Dual Simplex IP Generation stage of the Compiler to generate the dual simplex IP for synthesis.

To use the DS Assignment Editor to assign DS groups, follow these steps:

  1. Open a Quartus® Prime Pro Edition project that targets the Agilex™ 5 device and includes a Platform Designer system that contains HSSI IP that support dual simplex mode.
  2. In Compilation Dashboard, click the IP Generation stage. The Messages window reports when generation is complete.
    Figure 3. IP Generation Stage in Compilation Dashboard


  3. Click Assignments > Dual Simplex (DS) Assignment Editor. The DS Assignment Editor opens listing all supported dual simplex IP in your design in the IP List and any existing DS assignments under DS Groups.
    Figure 4. DS Assignment Editor Before Creating DS Groups


  4. Create dual simplex groups and assign IP instances in DS Assignment Editor:
    • Right-click any instance under IP List and click Create instance in > New DS group.
    • Double-click the Name cell under DS Groups and type a new group name.
    • Right-click the DS Groups row and select Create DS Group.
    • Double-click any DS Group name to specify a unique DS group name that becomes the module name for the Verilog output.
    Figure 5. Dual Simplex (DS) Assignment Editor


  5. To place instances in a DS group, right-click the instance name and click Move to group. The visualizer shows the assigned channels and indicates any illegal assignments.
  6. Under Loopback Mode, double-click in the cell to optionally enable an available loopback mode for debug. NO_LOOPBACK is the default setting.
    Figure 6. Available Loopback Modes


  7. For any IP instance, double-click the Name cell to optionally specify a new instance name for the IP, and a Relative Offset from the origin location in units of channels.
  8. To specify shared clock properties within a DS group, select the instance under DS Groups, turn on Shared Clock, and specify the IP Port and Merge Port
    Figure 7. Specifying Shared Clock Properties


  9. View the DS assignments in the visualizer display of the Current Group. The visualizer and the Message panel indicate any illegal assignments. The visualizer display shows two rectangles that represent the simplex IP in two channels. These rectangles represent the Tx and Rx channels, respectively. You can select the Current Group that you want to visualize. Illegal assignments appear with red shading in the rectangle, and an error message displays in the Message panel.
    Figure 8. Illegal DS Group Assignment in the Assignment Visualizer


  10. When your DS assignments are complete, click the Save Assignments button to save the DS assignments to the .qsf for application during subsequent compilation stages.
  11. In the Compilation Dashboard, click HSSI Dual Simplex IP Generation to generate the dual simplex IP.
    Figure 9. HSSI Dual Simplex IP Generation Stage in Compilation Dashboard


    Note: HSSI Dual Simplex IP Generation is present in Compilation Dashboard only when targeting Agilex™ 5 FPGAs. For more information about dual simplex mode, refer to GTS Transceiver Dual-Simplex Interfaces User Guide.
Related Information
Level Two Title