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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor
1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor
1.1.2.4. Specify I/O Constraints in Pin Planner
1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.6. Adjust Constraints with the Chip Planner
1.1.2.7. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups
3.2.2. Assigning Slew Rate and Drive Strength
3.2.3. Assigning I/O Banks
3.2.4. Changing Pin Planner Highlight Colors
3.2.5. Showing I/O Lanes
3.2.6. Assigning Differential Pins
3.2.7. Entering Pin Assignments with Tcl Commands
3.2.8. Entering Pin Assignments in HDL Code
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2.1.4.2. Report Pins
Generate reports about I/O pins in the design. Right-click any cell type to place, unplace, or report connectivity or location information.
Command | Description |
---|---|
Report All Placed Pins | Generates the Placed Pins report. This report lists the name, parent, type, and location of all placed pins in the interface plan. |
Report All Unplaced Pins | Generates the Unplaced Pins report. This report lists the name, parent, type, and the number of potential placements for all unplaced pins in the interface plan. |
Figure 25. Placed Pins Report
Figure 26. Unplaced Pins Report