Visible to Intel only — GUID: mwh1410471037587
Ixiasoft
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor
1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor
1.1.2.4. Specify I/O Constraints in Pin Planner
1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.6. Adjust Constraints with the Chip Planner
1.1.2.7. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups
3.2.2. Assigning Slew Rate and Drive Strength
3.2.3. Assigning I/O Banks
3.2.4. Changing Pin Planner Highlight Colors
3.2.5. Showing I/O Lanes
3.2.6. Assigning Differential Pins
3.2.7. Entering Pin Assignments with Tcl Commands
3.2.8. Entering Pin Assignments in HDL Code
Visible to Intel only — GUID: mwh1410471037587
Ixiasoft
3.1.1. Basic I/O Planning Flow
The following steps describe the basic flow for assigning and verifying I/O pin assignments:
- Click Assignments > Device and select a target device that meets your logic, performance, and I/O requirements. Consider and specify I/O standards, voltage and power supply requirements, and available I/O pins.
- Click Assignments > Pin Planner.
- Assign I/O properties to match your device and PCB characteristics, including assigning logic, I/O standards, output loading, slew rate, and current strength.
- Click Run I/O Assignment Analysis in the Tasks pane to validate assignments and generate a synthesized design netlist. Correct any problems reported.
- Click Processing > Start Compilation. During compilation, the Quartus® Prime software runs I/O assignment analysis.