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2.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
2.1.2.2. Specify NoC Constraints in NoC Assignment Editor
2.1.2.3. Specify I/O Constraints in Pin Planner
2.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
2.1.2.5. Adjust Constraints with the Chip Planner
2.1.2.6. Constraining Designs with the Design Partition Planner
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2.2.4. Synopsys* Design Constraint (.sdc) Files
Intel® Quartus® Prime software keeps timing constraints in .sdc files, which use Tcl syntax. You can embed these constraints in a scripted compilation flow, and even create sets of .sdc files for timing optimization.
.sdc File
The example shows the timing constrains of a small design.
## PROGRAM "Quartus Prime" ## VERSION "Version 17.1.0 Internal Build 91 05/07/2017 SJ Pro Edition" ## DATE "Wed May 10 14:22:08 2017" ## ## DEVICE "10AX115R4F40I3SG" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clk_in} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk_in}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -clock [get_clocks {clk_in}] 1.500 [get_ports {async_rst}] set_input_delay -add_delay -clock [get_clocks {clk_in}] 1.200 [get_ports {data_in}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -clock [get_clocks {clk_in}] 2.000 [get_ports {data_out}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -from [get_keepers *] -to [get_keepers {reg2}] 2