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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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3.8. Managing Device I/O Pins Revision History
The following table shows the revision history for this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2022.04.27 | 22.1 | Made a minor fix. |
2020.11.04 | 19.3 | Removed references to obsolete FPGA Xchange file (.fx) support from "Integrating PCB Design Tools" and "Importing and Exporting I/O Pin Assignments" topics. |
2018.05.07 | 18.0 |
|
2017.11.06 | 17.1 |
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2017.05.08 | 17.0 |
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2016.10.31 | 16.1 |
|
2015.11.02 | 15.1 |
|
2014.12.15 | 14.1 |
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2014.08.30 | 14.0a10 |
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2014.06.30 | 14.0 |
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November 2013 | 13.1 |
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May 2013 | 13.0 |
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November 2012 | 12.1 |
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June 2012 | 12.0.0 |
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November 2011 | 11.1 |
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December 2010 | 10.0 | Template update |
July 2010 | 10.0 |
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November 2009 | 9.1 |
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March 2009 | 9.0 |
|