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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specifying Multi-Dimensional Bus Constraints
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
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1.4. Constraining Designs Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
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2021.10.04 | 21.3 |
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2019.10.16 | 19.3 |
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2019.08.21 | 18.1 | Corrected minor typo in "Tcl-only Script Flows" topic. |
2019.01.04 | 18.1 |
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2017.11.06 | 17.1 |
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2017.05.08 | 17.0 |
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2016.10.31 | 16.1 |
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2015.11.02 | 15.1 |
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June 2014 | 14.0 | Formatting updates. |
November 2012 | 12.1 | Update Pin Planner description for task and report windows. |
June 2012 | 12.0 | Removed survey link. |
November 2011 | 10.0 | Template update. |
December 2010 | 10.0 | Template update. |
July 2010 | 10.0 | Rewrote chapter to more broadly cover all design constraint methods. Removed procedural steps and user interface details, and replaced with links to Quartus II Help. |
November 2009 | 9.1 |
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March 2009 | 9.0 |
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November 2008 | 8.1 | Changed to 8½” × 11” page size. No change to content. |
May 2008 | 8.0 | Updated Quartus II software 8.0 revision and date. |